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2f1f7a5f8a
Qualcom's new core, oryon-1, has a different characteristics for memset than the current versions of memset. For non-zero, larger sizes, using GPRs rather than the SIMD stores is ~30% faster. For even larger sizes, using the nontemporal stores is needed not to polute the L1/L2 caches. For zero values, using `dc zva` should be used. Since we know the size will always be 64 bytes, we don't need to figure out the size there. I started with the emag memset and added back the `dc zva` code. Changes since v1: * v3: Fix comment formating Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com> Reviewed-by: Adhemerval Zanella <adhemerval.zanella@linaro.org>
170 lines
4.1 KiB
ArmAsm
170 lines
4.1 KiB
ArmAsm
/* Optimized memset for Qualcomm's oyron-1 core.
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Copyright (C) 2018-2024 Free Software Foundation, Inc.
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Copyright The GNU Toolchain Authors.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library. If not, see
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<https://www.gnu.org/licenses/>. */
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#include <sysdep.h>
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#include "memset-reg.h"
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/* Assumptions:
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ARMv8-a, AArch64, unaligned accesses
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*/
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ENTRY (__memset_oryon1)
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PTR_ARG (0)
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SIZE_ARG (2)
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bfi valw, valw, 8, 8
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bfi valw, valw, 16, 16
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bfi val, val, 32, 32
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add dstend, dstin, count
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cmp count, 96
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b.hi L(set_long)
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cmp count, 16
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b.hs L(set_medium)
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/* Set 0..15 bytes. */
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tbz count, 3, 1f
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str val, [dstin]
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str val, [dstend, -8]
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ret
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.p2align 3
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1: tbz count, 2, 2f
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str valw, [dstin]
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str valw, [dstend, -4]
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ret
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2: cbz count, 3f
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strb valw, [dstin]
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tbz count, 1, 3f
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strh valw, [dstend, -2]
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3: ret
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.p2align 3
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/* Set 16..96 bytes. */
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L(set_medium):
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stp val, val, [dstin]
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tbnz count, 6, L(set96)
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stp val, val, [dstend, -16]
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tbz count, 5, 1f
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stp val, val, [dstin, 16]
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stp val, val, [dstend, -32]
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1: ret
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.p2align 6
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/* Set 64..96 bytes. Write 64 bytes from the start and
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32 bytes from the end. */
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L(set96):
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stp val, val, [dstin, 16]
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stp val, val, [dstin, 32]
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stp val, val, [dstin, 48]
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stp val, val, [dstend, -32]
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stp val, val, [dstend, -16]
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ret
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.p2align 6
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L(set_long):
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stp val, val, [dstin]
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bic dst, dstin, 15
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cmp count, 256
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ccmp valw, 0, 0, cs
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b.eq L(try_zva)
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cmp count, #32768
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b.hi L(set_long_with_nontemp)
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/* Small-size or non-zero memset does not use DC ZVA. */
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sub count, dstend, dst
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/* Adjust count and bias for loop. By subtracting extra 1 from count,
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it is easy to use tbz instruction to check whether loop tailing
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count is less than 33 bytes, so as to bypass 2 unnecessary stps. */
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sub count, count, 64+16+1
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1: stp val, val, [dst, 16]
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stp val, val, [dst, 32]
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stp val, val, [dst, 48]
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stp val, val, [dst, 64]!
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subs count, count, 64
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b.hs 1b
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tbz count, 5, 1f /* Remaining count is less than 33 bytes? */
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stp val, val, [dst, 16]
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stp val, val, [dst, 32]
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1: stp val, val, [dstend, -32]
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stp val, val, [dstend, -16]
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ret
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L(set_long_with_nontemp):
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/* Small-size or non-zero memset does not use DC ZVA. */
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sub count, dstend, dst
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/* Adjust count and bias for loop. By subtracting extra 1 from count,
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it is easy to use tbz instruction to check whether loop tailing
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count is less than 33 bytes, so as to bypass 2 unnecessary stps. */
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sub count, count, 64+16+1
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1: stnp val, val, [dst, 16]
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stnp val, val, [dst, 32]
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stnp val, val, [dst, 48]
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stnp val, val, [dst, 64]
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add dst, dst, #64
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subs count, count, 64
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b.hs 1b
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tbz count, 5, 1f /* Remaining count is less than 33 bytes? */
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stnp val, val, [dst, 16]
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stnp val, val, [dst, 32]
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1: stnp val, val, [dstend, -32]
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stnp val, val, [dstend, -16]
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ret
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L(try_zva):
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/* Write the first and last 64 byte aligned block using stp rather
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than using DC ZVA as it is faster. */
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.p2align 6
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L(zva_64):
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stp val, val, [dst, 16]
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stp val, val, [dst, 32]
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stp val, val, [dst, 48]
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bic dst, dst, 63
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stp val, val, [dst, 64]
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stp val, val, [dst, 64+16]
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stp val, val, [dst, 96]
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stp val, val, [dst, 96+16]
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sub count, dstend, dst /* Count is now 128 too large. */
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sub count, count, 128+64+64 /* Adjust count and bias for loop. */
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add dst, dst, 128
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1: dc zva, dst
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add dst, dst, 64
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subs count, count, 64
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b.hi 1b
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stp val, val, [dst, 0]
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stp val, val, [dst, 16]
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stp val, val, [dst, 32]
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stp val, val, [dst, 48]
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stp val, val, [dstend, -64]
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stp val, val, [dstend, -64+16]
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stp val, val, [dstend, -32]
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stp val, val, [dstend, -16]
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ret
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END (__memset_oryon1)
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