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a6b7502ec0
No bug.
The optimizations are as follows:
1) Always align entry to 64 bytes. This makes behavior more
predictable and makes other frontend optimizations easier.
2) Make the L(more_8x_vec) cases 4k aliasing aware. This can have
significant benefits in the case that:
0 < (dst - src) < [256, 512]
3) Align before `rep movsb`. For ERMS this is roughly a [0, 30%]
improvement and for FSRM [-10%, 25%].
In addition to these primary changes there is general cleanup
throughout to optimize the aligning routines and control flow logic.
Signed-off-by: Noah Goldstein <goldstein.w.n@gmail.com>
Reviewed-by: H.J. Lu <hjl.tools@gmail.com>
34 lines
732 B
ArmAsm
34 lines
732 B
ArmAsm
#if IS_IN (libc)
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# define VEC_SIZE 64
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# define XMM0 xmm16
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# define XMM1 xmm17
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# define YMM0 ymm16
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# define YMM1 ymm17
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# define VEC0 zmm16
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# define VEC1 zmm17
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# define VEC2 zmm18
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# define VEC3 zmm19
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# define VEC4 zmm20
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# define VEC5 zmm21
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# define VEC6 zmm22
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# define VEC7 zmm23
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# define VEC8 zmm24
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# define VEC9 zmm25
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# define VEC10 zmm26
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# define VEC11 zmm27
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# define VEC12 zmm28
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# define VEC13 zmm29
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# define VEC14 zmm30
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# define VEC15 zmm31
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# define VEC(i) VEC##i
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# define VMOVNT vmovntdq
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# define VMOVU vmovdqu64
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# define VMOVA vmovdqa64
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# define VZEROUPPER
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# define MOV_SIZE 6
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# define SECTION(p) p##.evex512
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# define MEMMOVE_SYMBOL(p,s) p##_avx512_##s
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# include "memmove-vec-unaligned-erms.S"
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#endif
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