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Similar to other CPU feature checks, check if SSE is available with HAS_CPU_FEATURE. * sysdeps/i386/fpu/fclrexcpt.c (__feclearexcept): Use HAS_CPU_FEATURE to check for SSE. * sysdeps/i386/fpu/fedisblxcpt.c (fedisableexcept): Likewise. * sysdeps/i386/fpu/feenablxcpt.c (feenableexcept): Likewise. * sysdeps/i386/fpu/fegetenv.c (__fegetenv): Likewise. * sysdeps/i386/fpu/fegetmode.c (fegetmode): Likewise. * sysdeps/i386/fpu/feholdexcpt.c (__feholdexcept): Likewise. * sysdeps/i386/fpu/fesetenv.c (__fesetenv): Likewise. * sysdeps/i386/fpu/fesetmode.c (fesetmode): Likewise. * sysdeps/i386/fpu/fesetround.c (__fesetround): Likewise. * sysdeps/i386/fpu/feupdateenv.c (__feupdateenv): Likewise. * sysdeps/i386/fpu/fgetexcptflg.c (__fegetexceptflag): Likewise. * sysdeps/i386/fpu/fsetexcptflg.c (__fesetexceptflag): Likewise. * sysdeps/i386/fpu/ftestexcept.c (fetestexcept): Likewise. * sysdeps/i386/setfpucw.c (__setfpucw): Likewise. * sysdeps/x86/cpu-features.h (bit_cpu_SSE): New. (index_cpu_SSE): Likewise. (reg_SSE): Likewise.
55 lines
1.7 KiB
C
55 lines
1.7 KiB
C
/* Install given floating-point control modes. i386 version.
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Copyright (C) 2016-2017 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<http://www.gnu.org/licenses/>. */
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#include <fenv.h>
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#include <fpu_control.h>
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#include <unistd.h>
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#include <ldsodefs.h>
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#include <dl-procinfo.h>
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/* All exceptions, including the x86-specific "denormal operand"
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exception. */
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#define FE_ALL_EXCEPT_X86 (FE_ALL_EXCEPT | __FE_DENORM)
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int
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fesetmode (const femode_t *modep)
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{
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fpu_control_t cw;
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if (modep == FE_DFL_MODE)
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cw = _FPU_DEFAULT;
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else
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cw = modep->__control_word;
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_FPU_SETCW (cw);
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if (HAS_CPU_FEATURE (SSE))
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{
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unsigned int mxcsr;
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__asm__ ("stmxcsr %0" : "=m" (mxcsr));
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/* Preserve SSE exception flags but restore other state in
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MXCSR. */
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mxcsr &= FE_ALL_EXCEPT_X86;
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if (modep == FE_DFL_MODE)
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/* Default MXCSR state has all bits zero except for those
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masking exceptions. */
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mxcsr |= FE_ALL_EXCEPT_X86 << 7;
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else
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mxcsr |= modep->__mxcsr & ~FE_ALL_EXCEPT_X86;
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__asm__ ("ldmxcsr %0" : : "m" (mxcsr));
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}
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return 0;
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}
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