glibc/sysdeps/aarch64/fpu/Versions
Joe Ramsay 31aaf6fed9 aarch64: Add vector implementations of exp10 routines
Double-precision routines either reuse the exp table (AdvSIMD) or use
SVE FEXPA intruction.
2023-10-23 15:00:45 +01:00

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libmvec {
GLIBC_2.38 {
_ZGVnN2v_cos;
_ZGVnN2v_exp;
_ZGVnN2v_log;
_ZGVnN2v_sin;
_ZGVnN4v_cosf;
_ZGVnN4v_expf;
_ZGVnN4v_logf;
_ZGVnN4v_sinf;
_ZGVsMxv_cos;
_ZGVsMxv_cosf;
_ZGVsMxv_exp;
_ZGVsMxv_expf;
_ZGVsMxv_log;
_ZGVsMxv_logf;
_ZGVsMxv_sin;
_ZGVsMxv_sinf;
}
GLIBC_2.39 {
_ZGVnN4v_exp10f;
_ZGVnN2v_exp10;
_ZGVsMxv_exp10f;
_ZGVsMxv_exp10;
_ZGVnN4v_exp2f;
_ZGVnN2v_exp2;
_ZGVsMxv_exp2f;
_ZGVsMxv_exp2;
_ZGVnN4v_log10f;
_ZGVnN2v_log10;
_ZGVsMxv_log10f;
_ZGVsMxv_log10;
_ZGVnN4v_log2f;
_ZGVnN2v_log2;
_ZGVsMxv_log2f;
_ZGVsMxv_log2;
_ZGVnN4v_tanf;
_ZGVnN2v_tan;
_ZGVsMxv_tanf;
_ZGVsMxv_tan;
}
}