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__fe_nomask_env. * sysdeps/powerpc/fpu/fe_nomask.c: Add libm_hidden_def. * sysdeps/unix/sysv/linux/powerpc/powerpc32/fpu/fe_nomask.c: Likewise. * sysdeps/unix/sysv/linux/powerpc/powerpc64/fpu/fe_nomask.c: Likewise. * sysdeps/powerpc/bits/fenv.h: Make safe for C++. * sysdeps/unix/sysv/linux/powerpc/bits/mathinline.h: New file. * sysdeps/powerpc/fpu/fegetexcept.c (__fegetexcept): Rename function from fegetexcept and make old name weak alias. * include/fenv.h: Declare __fegetexcept. * sysdeps/powerpc/fpu/fedisblxcpt.c: Use __fegetexcept instead of fegetexcept. * sysdeps/powerpc/fpu/feenablxcpt.c: Likewise. * sysdeps/powerpc/fpu/fraiseexcpt.c (__feraiseexcept): Avoid call to fetestexcept. * sysdeps/ieee754/ldbl-128ibm/s_log1pl.c (__log1pl): Use __frexpl instead of frexpl to avoid local PLT. * math/s_significandl.c (__significandl): Use __ilogbl instead of ilogbl to avoid local PLT. * sysdeps/ieee754/ldbl-128ibm/s_expm1l.c (__expm1l): Use __ldexpl instead of ldexpl to avoid local PLT. * sysdeps/ieee754/ldbl-128ibm/e_expl.c (__ieee754_expl): Use __roundl not roundl to avoid local PLT. * sysdeps/ieee754/ldbl-128/e_j0l.c: Use function names which avoid local PLTs. Use __sincosl instead of separate sinl and cosl calls. * sysdeps/ieee754/ldbl-128/e_j1l.c: Likewise.
161 lines
5.8 KiB
C
161 lines
5.8 KiB
C
/* Copyright (C) 1997, 1998, 1999, 2008 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, write to the Free
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Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
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02111-1307 USA. */
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#ifndef _FENV_H
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# error "Never use <bits/fenv.h> directly; include <fenv.h> instead."
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#endif
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/* Define bits representing the exception. We use the bit positions of
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the appropriate bits in the FPSCR... */
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enum
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{
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FE_INEXACT = 1 << (31 - 6),
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#define FE_INEXACT FE_INEXACT
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FE_DIVBYZERO = 1 << (31 - 5),
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#define FE_DIVBYZERO FE_DIVBYZERO
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FE_UNDERFLOW = 1 << (31 - 4),
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#define FE_UNDERFLOW FE_UNDERFLOW
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FE_OVERFLOW = 1 << (31 - 3),
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#define FE_OVERFLOW FE_OVERFLOW
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/* ... except for FE_INVALID, for which we use bit 31. FE_INVALID
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actually corresponds to bits 7 through 12 and 21 through 23
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in the FPSCR, but we can't use that because the current draft
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says that it must be a power of 2. Instead we use bit 2 which
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is the summary bit for all the FE_INVALID exceptions, which
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kind of makes sense. */
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FE_INVALID = 1 << (31 - 2),
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#define FE_INVALID FE_INVALID
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#ifdef __USE_GNU
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/* Breakdown of the FE_INVALID bits. Setting FE_INVALID on an
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input to a routine is equivalent to setting all of these bits;
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FE_INVALID will be set on output from a routine iff one of
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these bits is set. Note, though, that you can't disable or
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enable these exceptions individually. */
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/* Operation with SNaN. */
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FE_INVALID_SNAN = 1 << (31 - 7),
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# define FE_INVALID_SNAN FE_INVALID_SNAN
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/* Inf - Inf */
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FE_INVALID_ISI = 1 << (31 - 8),
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# define FE_INVALID_ISI FE_INVALID_ISI
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/* Inf / Inf */
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FE_INVALID_IDI = 1 << (31 - 9),
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# define FE_INVALID_IDI FE_INVALID_IDI
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/* 0 / 0 */
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FE_INVALID_ZDZ = 1 << (31 - 10),
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# define FE_INVALID_ZDZ FE_INVALID_ZDZ
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/* Inf * 0 */
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FE_INVALID_IMZ = 1 << (31 - 11),
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# define FE_INVALID_IMZ FE_INVALID_IMZ
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/* Comparison with NaN or SNaN. */
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FE_INVALID_COMPARE = 1 << (31 - 12),
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# define FE_INVALID_COMPARE FE_INVALID_COMPARE
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/* Invalid operation flag for software (not set by hardware). */
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/* Note that some chips don't have this implemented, presumably
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because no-one expected anyone to write software for them %-). */
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FE_INVALID_SOFTWARE = 1 << (31 - 21),
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# define FE_INVALID_SOFTWARE FE_INVALID_SOFTWARE
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/* Square root of negative number (including -Inf). */
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/* Note that some chips don't have this implemented. */
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FE_INVALID_SQRT = 1 << (31 - 22),
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# define FE_INVALID_SQRT FE_INVALID_SQRT
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/* Conversion-to-integer of a NaN or a number too large or too small. */
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FE_INVALID_INTEGER_CONVERSION = 1 << (31 - 23)
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# define FE_INVALID_INTEGER_CONVERSION FE_INVALID_INTEGER_CONVERSION
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# define FE_ALL_INVALID \
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(FE_INVALID_SNAN | FE_INVALID_ISI | FE_INVALID_IDI | FE_INVALID_ZDZ \
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| FE_INVALID_IMZ | FE_INVALID_COMPARE | FE_INVALID_SOFTWARE \
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| FE_INVALID_SQRT | FE_INVALID_INTEGER_CONVERSION)
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#endif
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};
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#define FE_ALL_EXCEPT \
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(FE_INEXACT | FE_DIVBYZERO | FE_UNDERFLOW | FE_OVERFLOW | FE_INVALID)
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/* PowerPC chips support all of the four defined rounding modes. We
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use the bit pattern in the FPSCR as the values for the
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appropriate macros. */
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enum
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{
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FE_TONEAREST = 0,
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#define FE_TONEAREST FE_TONEAREST
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FE_TOWARDZERO = 1,
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#define FE_TOWARDZERO FE_TOWARDZERO
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FE_UPWARD = 2,
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#define FE_UPWARD FE_UPWARD
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FE_DOWNWARD = 3
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#define FE_DOWNWARD FE_DOWNWARD
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};
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/* Type representing exception flags. */
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typedef unsigned int fexcept_t;
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/* Type representing floating-point environment. We leave it as 'double'
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for efficiency reasons (rather than writing it to a 32-bit integer). */
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typedef double fenv_t;
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/* If the default argument is used we use this value. */
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extern const fenv_t __fe_dfl_env;
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#define FE_DFL_ENV (&__fe_dfl_env)
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#ifdef __USE_GNU
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/* Floating-point environment where all exceptions are enabled. Note that
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this is not sufficient to give you SIGFPE. */
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extern const fenv_t __fe_enabled_env;
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# define FE_ENABLED_ENV (&__fe_enabled_env)
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/* Floating-point environment with (processor-dependent) non-IEEE floating
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point. */
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extern const fenv_t __fe_nonieee_env;
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# define FE_NONIEEE_ENV (&__fe_nonieee_env)
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__BEGIN_DECLS
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/* Floating-point environment with all exceptions enabled. Note that
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just evaluating this value does not change the processor exception mode.
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Passing this mask to fesetenv will result in a prctl syscall to change
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the MSR FE0/FE1 bits to "Precise Mode". On some processors this will
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result in slower floating point execution. This will last until an
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fenv or exception mask is installed that disables all FP exceptions. */
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extern const fenv_t *__fe_nomask_env (void);
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# define FE_NOMASK_ENV FE_ENABLED_ENV
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/* Floating-point environment with all exceptions disabled. Note that
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just evaluating this value does not change the processor exception mode.
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Passing this mask to fesetenv will result in a prctl syscall to change
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the MSR FE0/FE1 bits to "Ignore Exceptions Mode". On most processors
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this allows the fastest possible floating point execution.*/
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extern const fenv_t *__fe_mask_env (void);
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# define FE_MASK_ENV FE_DFL_ENV
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__END_DECLS
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#endif
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