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408 lines
10 KiB
C
408 lines
10 KiB
C
/* Get file-specific information about a file. Linux version.
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Copyright (C) 2003, 2004 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, write to the Free
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Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
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02111-1307 USA. */
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#include <assert.h>
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#include <stdbool.h>
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#include <stdlib.h>
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#include <unistd.h>
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#include <hp-timing.h>
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static long int linux_sysconf (int name);
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static long int
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handle_i486 (int name)
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{
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/* The processor only has a unified level 1 cache of 8k. */
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switch (name)
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{
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case _SC_LEVEL1_ICACHE_SIZE:
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case _SC_LEVEL1_DCACHE_SIZE:
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return 8 * 1024;
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case _SC_LEVEL1_ICACHE_ASSOC:
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case _SC_LEVEL1_DCACHE_ASSOC:
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// XXX Anybody know this?
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return 0;
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case _SC_LEVEL1_ICACHE_LINESIZE:
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case _SC_LEVEL1_DCACHE_LINESIZE:
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// XXX Anybody know for sure?
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return 16;
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case _SC_LEVEL2_CACHE_SIZE:
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case _SC_LEVEL2_CACHE_ASSOC:
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case _SC_LEVEL2_CACHE_LINESIZE:
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case _SC_LEVEL3_CACHE_SIZE:
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case _SC_LEVEL3_CACHE_ASSOC:
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case _SC_LEVEL3_CACHE_LINESIZE:
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case _SC_LEVEL4_CACHE_SIZE:
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case _SC_LEVEL4_CACHE_ASSOC:
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/* Not available. */
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break;
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default:
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assert (! "cannot happen");
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}
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return -1;
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}
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static const struct intel_02_cache_info
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{
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unsigned int idx;
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int name;
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long int size;
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long int assoc;
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long int linesize;
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} intel_02_known[] =
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{
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{ 0x06, _SC_LEVEL1_ICACHE_SIZE, 8192, 4, 32 },
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{ 0x08, _SC_LEVEL1_ICACHE_SIZE, 16384, 4, 32 },
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{ 0x0a, _SC_LEVEL1_DCACHE_SIZE, 8192, 2, 32 },
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{ 0x0c, _SC_LEVEL1_DCACHE_SIZE, 16384, 4, 32 },
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{ 0x22, _SC_LEVEL3_CACHE_SIZE, 524288, 4, 64 },
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{ 0x23, _SC_LEVEL3_CACHE_SIZE, 1048576, 8, 64 },
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{ 0x25, _SC_LEVEL3_CACHE_SIZE, 2097152, 8, 64 },
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{ 0x29, _SC_LEVEL3_CACHE_SIZE, 4194304, 8, 64 },
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{ 0x2c, _SC_LEVEL1_DCACHE_SIZE, 32768, 8, 64 },
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{ 0x30, _SC_LEVEL1_ICACHE_SIZE, 32768, 8, 64 },
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{ 0x41, _SC_LEVEL2_CACHE_SIZE, 131072, 4, 32 },
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{ 0x42, _SC_LEVEL2_CACHE_SIZE, 262144, 4, 32 },
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{ 0x43, _SC_LEVEL2_CACHE_SIZE, 524288, 4, 32 },
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{ 0x44, _SC_LEVEL2_CACHE_SIZE, 1048576, 4, 32 },
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{ 0x45, _SC_LEVEL2_CACHE_SIZE, 2097152, 4, 32 },
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{ 0x60, _SC_LEVEL1_DCACHE_SIZE, 16384, 8, 64 },
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{ 0x66, _SC_LEVEL1_DCACHE_SIZE, 8192, 4, 64 },
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{ 0x67, _SC_LEVEL1_DCACHE_SIZE, 16384, 4, 64 },
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{ 0x68, _SC_LEVEL1_DCACHE_SIZE, 32768, 4, 64 },
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{ 0x78, _SC_LEVEL2_CACHE_SIZE, 1048576, 8, 64 },
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{ 0x79, _SC_LEVEL2_CACHE_SIZE, 131072, 8, 64 },
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{ 0x7a, _SC_LEVEL2_CACHE_SIZE, 262144, 8, 64 },
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{ 0x7b, _SC_LEVEL2_CACHE_SIZE, 524288, 8, 64 },
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{ 0x7c, _SC_LEVEL2_CACHE_SIZE, 1048576, 8, 64 },
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{ 0x7d, _SC_LEVEL2_CACHE_SIZE, 2097152, 8, 64 },
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{ 0x82, _SC_LEVEL2_CACHE_SIZE, 262144, 8, 32 },
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{ 0x83, _SC_LEVEL2_CACHE_SIZE, 524288, 8, 32 },
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{ 0x84, _SC_LEVEL2_CACHE_SIZE, 1048576, 8, 32 },
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{ 0x85, _SC_LEVEL2_CACHE_SIZE, 2097152, 8, 32 },
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{ 0x86, _SC_LEVEL2_CACHE_SIZE, 524288, 4, 64 },
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{ 0x87, _SC_LEVEL2_CACHE_SIZE, 1048576, 8, 64 },
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};
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#define nintel_02_known (sizeof (intel_02_known) / sizeof (intel_02_known[0]))
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static int
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intel_02_known_compare (const void *p1, const void *p2)
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{
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const struct intel_02_cache_info *i1;
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const struct intel_02_cache_info *i2;
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i1 = (const struct intel_02_cache_info *) p1;
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i2 = (const struct intel_02_cache_info *) p2;
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if (i1->idx == i2->idx)
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return 0;
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return i1->idx < i2->idx ? -1 : 1;
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}
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static long int
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intel_check_word (int name, unsigned int value, bool *has_level_2,
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bool *no_level_2_or_3)
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{
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if ((value & 0x80000000) != 0)
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/* The register value is reserved. */
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return 0;
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/* Fold the name. The _SC_ constants are always in the order SIZE,
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ASSOC, LINESIZE. */
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int folded_name = (_SC_LEVEL1_ICACHE_SIZE
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+ ((name - _SC_LEVEL1_ICACHE_SIZE) / 3) * 3);
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while (value != 0)
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{
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unsigned int byte = value & 0xff;
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if (byte == 0x40)
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{
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*no_level_2_or_3 = true;
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if (folded_name == _SC_LEVEL3_CACHE_SIZE)
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/* No need to look further. */
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break;
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}
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else
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{
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struct intel_02_cache_info *found;
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struct intel_02_cache_info search;
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search.idx = byte;
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found = bsearch (&search, intel_02_known, nintel_02_known,
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sizeof (intel_02_known[0]), intel_02_known_compare);
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if (found != NULL)
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{
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if (found->name == folded_name)
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{
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unsigned int offset = name - folded_name;
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if (offset == 0)
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/* Cache size. */
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return found->size;
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if (offset == 1)
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return found->assoc;
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assert (offset == 2);
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return found->linesize;
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}
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if (found->name == _SC_LEVEL2_CACHE_SIZE)
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*has_level_2 = true;
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}
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}
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/* Next byte for the next round. */
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value >>= 8;
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}
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/* Nothing found. */
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return 0;
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}
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static long int
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handle_intel (int name, unsigned int maxidx)
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{
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if (maxidx < 2)
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{
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// XXX Do such processors exist? When we know we can fill in some
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// values.
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return 0;
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}
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/* OK, we can use the CPUID instruction to get all info about the
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caches. */
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unsigned int cnt = 0;
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unsigned int max = 1;
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long int result = 0;
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bool no_level_2_or_3 = false;
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bool has_level_2 = false;
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while (cnt++ < max)
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{
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unsigned int eax;
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unsigned int ebx;
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unsigned int ecx;
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unsigned int edx;
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asm volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1"
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: "=a" (eax), "=r" (ebx), "=c" (ecx), "=d" (edx)
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: "0" (2));
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/* The low byte of EAX in the first round contain the number of
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rounds we have to make. At least one, the one we are already
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doing. */
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if (cnt == 1)
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{
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max = eax & 0xff;
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eax &= 0xffffff00;
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}
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/* Process the individual registers' value. */
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result = intel_check_word (name, eax, &has_level_2, &no_level_2_or_3);
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if (result != 0)
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return result;
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result = intel_check_word (name, ebx, &has_level_2, &no_level_2_or_3);
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if (result != 0)
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return result;
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result = intel_check_word (name, ecx, &has_level_2, &no_level_2_or_3);
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if (result != 0)
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return result;
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result = intel_check_word (name, edx, &has_level_2, &no_level_2_or_3);
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if (result != 0)
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return result;
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}
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if (name >= _SC_LEVEL2_CACHE_SIZE && name <= _SC_LEVEL3_CACHE_LINESIZE
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&& no_level_2_or_3)
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return -1;
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return 0;
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}
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static long int
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handle_amd (int name)
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{
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unsigned int eax;
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unsigned int ebx;
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unsigned int ecx;
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unsigned int edx;
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asm volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1"
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: "=a" (eax), "=r" (ebx), "=c" (ecx), "=d" (edx)
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: "0" (0x80000000));
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if (name >= _SC_LEVEL3_CACHE_SIZE)
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return 0;
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unsigned int fn = 0x80000005 + (name >= _SC_LEVEL2_CACHE_SIZE);
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if (eax < fn)
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return 0;
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asm volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1"
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: "=a" (eax), "=r" (ebx), "=c" (ecx), "=d" (edx)
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: "0" (fn));
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if (name < _SC_LEVEL1_DCACHE_SIZE)
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{
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name += _SC_LEVEL1_DCACHE_SIZE - _SC_LEVEL1_ICACHE_SIZE;
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ecx = edx;
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}
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switch (name)
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{
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case _SC_LEVEL1_DCACHE_SIZE:
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return (ecx >> 14) & 0x3fc00;
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case _SC_LEVEL1_DCACHE_ASSOC:
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ecx >>= 16;
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if ((ecx & 0xff) == 0xff)
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/* Fully associative. */
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return (ecx << 2) & 0x3fc00;
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return ecx & 0xff;
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case _SC_LEVEL1_DCACHE_LINESIZE:
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return ecx & 0xff;
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case _SC_LEVEL2_CACHE_SIZE:
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return (ecx & 0xf000) == 0 ? 0 : (ecx >> 6) & 0x3fffc00;
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case _SC_LEVEL2_CACHE_ASSOC:
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ecx >>= 12;
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switch (ecx & 0xf)
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{
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case 0:
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case 1:
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case 2:
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case 4:
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return ecx & 0xf;
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case 6:
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return 8;
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case 8:
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return 16;
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case 0xf:
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return (ecx << 6) & 0x3fffc00;
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default:
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return 0;
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}
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case _SC_LEVEL2_CACHE_LINESIZE:
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return (ecx & 0xf000) == 0 ? 0 : ecx & 0xff;
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default:
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assert (! "cannot happen");
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}
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return -1;
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}
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static int
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i386_i486_test (void)
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{
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int eflags;
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int ac;
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asm volatile ("pushfl;\n\t"
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"popl %0;\n\t"
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"movl $0x240000, %1;\n\t"
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"xorl %0, %1;\n\t"
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"pushl %1;\n\t"
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"popfl;\n\t"
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"pushfl;\n\t"
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"popl %1;\n\t"
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"xorl %0, %1;\n\t"
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"pushl %0;\n\t"
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"popfl"
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: "=r" (eflags), "=r" (ac));
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return ac;
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}
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/* Get the value of the system variable NAME. */
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long int
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__sysconf (int name)
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{
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if (name == _SC_CPUTIME || name == _SC_THREAD_CPUTIME)
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{
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#if HP_TIMING_AVAIL
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// XXX We can add here test for machines which cannot support a
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// XXX usable TSC.
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return 200112L;
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#else
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return -1;
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#endif
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}
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/* All the remainder, except the cache information, is handled in
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the generic code. */
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if (name < _SC_LEVEL1_ICACHE_SIZE || name > _SC_LEVEL4_CACHE_LINESIZE)
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return linux_sysconf (name);
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/* Recognize i386 and compatible. These don't have any cache on
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board. */
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int ac = i386_i486_test ();
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if (ac == 0)
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/* This is an i386. */
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// XXX Is this true for all brands?
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return -1;
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/* Detect i486, the last Intel processor without CPUID. */
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if ((ac & (1 << 21)) == 0)
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{
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/* No CPUID. */
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// XXX Fill in info about other brands. For now only Intel.
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return handle_i486 (name);
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}
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/* Find out what brand of processor. */
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unsigned int eax;
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unsigned int ebx;
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unsigned int ecx;
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unsigned int edx;
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asm volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1"
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: "=a" (eax), "=r" (ebx), "=c" (ecx), "=d" (edx)
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: "0" (0));
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/* This spells out "GenuineIntel". */
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if (ebx == 0x756e6547 && ecx == 0x6c65746e && edx == 0x49656e69)
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return handle_intel (name, eax);
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/* This spells out "AuthenticAMD". */
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if (ebx == 0x68747541 && ecx == 0x444d4163 && edx == 0x69746e65)
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return handle_amd (name);
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// XXX Fill in more vendors.
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/* CPU not known, we have no information. */
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return 0;
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}
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/* Now the generic Linux version. */
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#undef __sysconf
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#define __sysconf static linux_sysconf
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#include "../sysconf.c"
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