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5a82c74822
Also, change sources.redhat.com to sourceware.org.
This patch was automatically generated by running the following shell
script, which uses GNU sed, and which avoids modifying files imported
from upstream:
sed -ri '
s,(http|ftp)(://(.*\.)?(gnu|fsf|sourceware)\.org($|[^.]|\.[^a-z])),https\2,g
s,(http|ftp)(://(.*\.)?)sources\.redhat\.com($|[^.]|\.[^a-z]),https\2sourceware.org\4,g
' \
$(find $(git ls-files) -prune -type f \
! -name '*.po' \
! -name 'ChangeLog*' \
! -path COPYING ! -path COPYING.LIB \
! -path manual/fdl-1.3.texi ! -path manual/lgpl-2.1.texi \
! -path manual/texinfo.tex ! -path scripts/config.guess \
! -path scripts/config.sub ! -path scripts/install-sh \
! -path scripts/mkinstalldirs ! -path scripts/move-if-change \
! -path INSTALL ! -path locale/programs/charmap-kw.h \
! -path po/libc.pot ! -path sysdeps/gnu/errlist.c \
! '(' -name configure \
-execdir test -f configure.ac -o -f configure.in ';' ')' \
! '(' -name preconfigure \
-execdir test -f preconfigure.ac ';' ')' \
-print)
and then by running 'make dist-prepare' to regenerate files built
from the altered files, and then executing the following to cleanup:
chmod a+x sysdeps/unix/sysv/linux/riscv/configure
# Omit irrelevant whitespace and comment-only changes,
# perhaps from a slightly-different Autoconf version.
git checkout -f \
sysdeps/csky/configure \
sysdeps/hppa/configure \
sysdeps/riscv/configure \
sysdeps/unix/sysv/linux/csky/configure
# Omit changes that caused a pre-commit check to fail like this:
# remote: *** error: sysdeps/powerpc/powerpc64/ppc-mcount.S: trailing lines
git checkout -f \
sysdeps/powerpc/powerpc64/ppc-mcount.S \
sysdeps/unix/sysv/linux/s390/s390-64/syscall.S
# Omit change that caused a pre-commit check to fail like this:
# remote: *** error: sysdeps/sparc/sparc64/multiarch/memcpy-ultra3.S: last line does not end in newline
git checkout -f sysdeps/sparc/sparc64/multiarch/memcpy-ultra3.S
91 lines
2.6 KiB
ArmAsm
91 lines
2.6 KiB
ArmAsm
/* RISC-V PLT trampoline
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Copyright (C) 2017-2019 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library. If not, see
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<https://www.gnu.org/licenses/>. */
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#include <sysdep.h>
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#include <sys/asm.h>
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/* Assembler veneer called from the PLT header code for lazy loading.
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The PLT header passes its own args in t0-t2. */
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#ifdef __riscv_float_abi_soft
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# define FRAME_SIZE (-((-10 * SZREG) & ALMASK))
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#else
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# define FRAME_SIZE (-((-10 * SZREG - 8 * SZFREG) & ALMASK))
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#endif
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ENTRY (_dl_runtime_resolve)
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# Save arguments to stack.
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addi sp, sp, -FRAME_SIZE
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REG_S ra, 9*SZREG(sp)
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REG_S a0, 1*SZREG(sp)
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REG_S a1, 2*SZREG(sp)
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REG_S a2, 3*SZREG(sp)
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REG_S a3, 4*SZREG(sp)
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REG_S a4, 5*SZREG(sp)
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REG_S a5, 6*SZREG(sp)
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REG_S a6, 7*SZREG(sp)
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REG_S a7, 8*SZREG(sp)
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#ifndef __riscv_float_abi_soft
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FREG_S fa0, (10*SZREG + 0*SZFREG)(sp)
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FREG_S fa1, (10*SZREG + 1*SZFREG)(sp)
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FREG_S fa2, (10*SZREG + 2*SZFREG)(sp)
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FREG_S fa3, (10*SZREG + 3*SZFREG)(sp)
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FREG_S fa4, (10*SZREG + 4*SZFREG)(sp)
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FREG_S fa5, (10*SZREG + 5*SZFREG)(sp)
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FREG_S fa6, (10*SZREG + 6*SZFREG)(sp)
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FREG_S fa7, (10*SZREG + 7*SZFREG)(sp)
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#endif
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# Update .got.plt and obtain runtime address of callee.
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slli a1, t1, 1
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mv a0, t0 # link map
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add a1, a1, t1 # reloc offset (== thrice the .got.plt offset)
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la a2, _dl_fixup
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jalr a2
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mv t1, a0
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# Restore arguments from stack.
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REG_L ra, 9*SZREG(sp)
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REG_L a0, 1*SZREG(sp)
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REG_L a1, 2*SZREG(sp)
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REG_L a2, 3*SZREG(sp)
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REG_L a3, 4*SZREG(sp)
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REG_L a4, 5*SZREG(sp)
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REG_L a5, 6*SZREG(sp)
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REG_L a6, 7*SZREG(sp)
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REG_L a7, 8*SZREG(sp)
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#ifndef __riscv_float_abi_soft
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FREG_L fa0, (10*SZREG + 0*SZFREG)(sp)
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FREG_L fa1, (10*SZREG + 1*SZFREG)(sp)
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FREG_L fa2, (10*SZREG + 2*SZFREG)(sp)
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FREG_L fa3, (10*SZREG + 3*SZFREG)(sp)
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FREG_L fa4, (10*SZREG + 4*SZFREG)(sp)
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FREG_L fa5, (10*SZREG + 5*SZFREG)(sp)
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FREG_L fa6, (10*SZREG + 6*SZFREG)(sp)
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FREG_L fa7, (10*SZREG + 7*SZFREG)(sp)
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#endif
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addi sp, sp, FRAME_SIZE
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# Invoke the callee.
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jr t1
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END (_dl_runtime_resolve)
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