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3c99806989
We found that string functions were using AND+ADDP to find the nibble/syndrome mask but there is an easier opportunity through `SHRN dst.8b, src.8h, 4` (shift right every 2 bytes by 4 and narrow to 1 byte) and has same latency on all SIMD ARMv8 targets as ADDP. There are also possible gaps for memcmp but that's for another patch. We see 10-20% savings for small-mid size cases (<=128) which are primary cases for general workloads.
90 lines
2.2 KiB
ArmAsm
90 lines
2.2 KiB
ArmAsm
/* Copyright (C) 2012-2022 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library. If not, see
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<https://www.gnu.org/licenses/>. */
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#include <sysdep.h>
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/* Assumptions:
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*
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* ARMv8-a, AArch64, Advanced SIMD.
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* MTE compatible.
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*/
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#ifndef STRLEN
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# define STRLEN __strlen
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#endif
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#define srcin x0
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#define result x0
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#define src x1
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#define synd x2
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#define tmp x3
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#define shift x4
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#define data q0
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#define vdata v0
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#define vhas_nul v1
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#define vend v2
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#define dend d2
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/* Core algorithm:
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For each 16-byte chunk we calculate a 64-bit nibble mask value with four bits
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per byte. We take 4 bits of every comparison byte with shift right and narrow
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by 4 instruction. Since the bits in the nibble mask reflect the order in
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which things occur in the original string, counting trailing zeros identifies
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exactly which byte matched. */
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ENTRY (STRLEN)
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PTR_ARG (0)
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bic src, srcin, 15
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ld1 {vdata.16b}, [src]
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cmeq vhas_nul.16b, vdata.16b, 0
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lsl shift, srcin, 2
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shrn vend.8b, vhas_nul.8h, 4 /* 128->64 */
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fmov synd, dend
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lsr synd, synd, shift
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cbz synd, L(loop)
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rbit synd, synd
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clz result, synd
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lsr result, result, 2
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ret
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.p2align 5
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L(loop):
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ldr data, [src, 16]!
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cmeq vhas_nul.16b, vdata.16b, 0
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umaxp vend.16b, vhas_nul.16b, vhas_nul.16b
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fmov synd, dend
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cbz synd, L(loop)
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shrn vend.8b, vhas_nul.8h, 4 /* 128->64 */
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sub result, src, srcin
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fmov synd, dend
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#ifndef __AARCH64EB__
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rbit synd, synd
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#endif
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clz tmp, synd
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add result, result, tmp, lsr 2
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ret
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END (STRLEN)
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weak_alias (STRLEN, strlen)
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libc_hidden_builtin_def (strlen)
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