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10cce66930
Replace inline asm uses of the "mffs" and "mtfsf" instructions with the analogous GCC builtins. __builtin_mffs and __builtin_mtfsf are both available in GCC 5 and above. Given the minimum GCC level for GLibC is now GCC 6.2, it is safe to use these builtins without restriction. 2019-03-29 Paul A. Clarke <pc@us.ibm.com> * sysdeps/powerpc/fpu/fenv_libc.h (fegetenv_register): Replace inline asm with builtin. * sysdeps/powerpc/powerpc64/le/fpu/sfp-machine.h (FP_INIT_ROUNDMODE): Likewise. * sysdeps/powerpc/fpu/tst-setcontext-fpscr.c (_GET_DI_FPSCR): Likewise. (_GET_SI_FPSCR): Likewise. (_SET_SI_FPSCR): Likewise.
115 lines
3.5 KiB
C
115 lines
3.5 KiB
C
#define _FP_W_TYPE_SIZE 64
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#define _FP_W_TYPE unsigned long long
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#define _FP_WS_TYPE signed long long
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#define _FP_I_TYPE long long
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typedef int TItype __attribute__ ((mode (TI)));
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typedef unsigned int UTItype __attribute__ ((mode (TI)));
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#define TI_BITS (__CHAR_BIT__ * (int) sizeof (TItype))
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/* The type of the result of a floating point comparison. This must
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match `__libgcc_cmp_return__' in GCC for the target. */
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typedef int __gcc_CMPtype __attribute__ ((mode (__libgcc_cmp_return__)));
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#define CMPtype __gcc_CMPtype
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#define _FP_MUL_MEAT_S(R,X,Y) \
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_FP_MUL_MEAT_1_wide(_FP_WFRACBITS_S,R,X,Y,umul_ppmm)
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#define _FP_MUL_MEAT_D(R,X,Y) \
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_FP_MUL_MEAT_1_wide(_FP_WFRACBITS_D,R,X,Y,umul_ppmm)
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#define _FP_MUL_MEAT_Q(R,X,Y) \
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_FP_MUL_MEAT_2_wide(_FP_WFRACBITS_Q,R,X,Y,umul_ppmm)
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#define _FP_DIV_MEAT_S(R,X,Y) _FP_DIV_MEAT_1_loop(S,R,X,Y)
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#define _FP_DIV_MEAT_D(R,X,Y) _FP_DIV_MEAT_1_udiv(D,R,X,Y)
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#define _FP_DIV_MEAT_Q(R,X,Y) _FP_DIV_MEAT_2_udiv(Q,R,X,Y)
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#define _FP_NANFRAC_S ((_FP_QNANBIT_S << 1) - 1)
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#define _FP_NANFRAC_D ((_FP_QNANBIT_D << 1) - 1)
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#define _FP_NANFRAC_Q ((_FP_QNANBIT_Q << 1) - 1), -1
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#define _FP_NANSIGN_S 0
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#define _FP_NANSIGN_D 0
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#define _FP_NANSIGN_Q 0
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#define _FP_KEEPNANFRACP 1
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#define _FP_QNANNEGATEDP 0
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/* Someone please check this. */
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#define _FP_CHOOSENAN(fs, wc, R, X, Y, OP) \
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do { \
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if ((_FP_FRAC_HIGH_RAW_##fs(X) & _FP_QNANBIT_##fs) \
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&& !(_FP_FRAC_HIGH_RAW_##fs(Y) & _FP_QNANBIT_##fs)) \
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{ \
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R##_s = Y##_s; \
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_FP_FRAC_COPY_##wc(R,Y); \
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} \
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else \
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{ \
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R##_s = X##_s; \
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_FP_FRAC_COPY_##wc(R,X); \
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} \
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R##_c = FP_CLS_NAN; \
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} while (0)
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#define _FP_TININESS_AFTER_ROUNDING 0
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#define __LITTLE_ENDIAN 1234
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#define __BIG_ENDIAN 4321
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#define __BYTE_ORDER __LITTLE_ENDIAN
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/* Only provide exception support if we have hardware floating point using
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floating point registers and we can execute the mtfsf instruction. This
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would only be true if we are using the emulation routines for IEEE 128-bit
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floating point on pre-ISA 3.0 machines without the IEEE 128-bit floating
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point support. */
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#ifdef __FLOAT128__
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#define ISA_BIT(x) (1LL << (63 - x))
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/* Use the same bits of the FPSCR. */
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# define FP_EX_INVALID ISA_BIT(34)
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# define FP_EX_OVERFLOW ISA_BIT(35)
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# define FP_EX_UNDERFLOW ISA_BIT(36)
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# define FP_EX_DIVZERO ISA_BIT(37)
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# define FP_EX_INEXACT ISA_BIT(38)
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# define FP_EX_ALL (FP_EX_INVALID | FP_EX_OVERFLOW \
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| FP_EX_UNDERFLOW | FP_EX_DIVZERO \
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| FP_EX_INEXACT)
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void __sfp_handle_exceptions (int);
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# define FP_HANDLE_EXCEPTIONS \
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do { \
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if (__builtin_expect (_fex, 0)) \
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__sfp_handle_exceptions (_fex); \
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} while (0);
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/* The FP_EX_* bits track whether the exception has occurred. This macro
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must set the FP_EX_* bits of those exceptions which are configured to
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trap. The FPSCR bit which indicates this is 22 ISA bits above the
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respective FP_EX_* bit. Note, the ISA labels bits from msb to lsb,
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so 22 ISA bits above is 22 bits below when counted from the lsb. */
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# define FP_TRAPPING_EXCEPTIONS ((_fpscr.i << 22) & FP_EX_ALL)
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# define FP_RND_NEAREST 0x0
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# define FP_RND_ZERO 0x1
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# define FP_RND_PINF 0x2
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# define FP_RND_MINF 0x3
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# define FP_RND_MASK 0x3
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# define _FP_DECL_EX \
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union { unsigned long long i; double d; } _fpscr __attribute__ ((unused)) = \
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{ .i = FP_RND_NEAREST }
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#define FP_INIT_ROUNDMODE \
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do { \
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_fpscr.d = __builtin_mffs (); \
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} while (0)
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# define FP_ROUNDMODE (_fpscr.i & FP_RND_MASK)
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#endif /* !__FLOAT128__ */
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