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3b5ebe85aa
This patch removes the arch-specific atomic instruction, relying on compiler builtins. The __sparc32_atomic_locks support is removed and a configure check is added to check if compiler uses libatomic to implement CAS. It also removes the sparc specific sem_* and pthread_barrier_* implementations. It in turn allows buidling against a LEON3/LEON4 sparcv8 target, although it will still be incompatible with generic sparcv9. Checked on sparcv9-linux-gnu and sparc64-linux-gnu. I also checked with build against sparcv8-linux-gnu with -mcpu=leon3. Tested-by: Andreas Larsson <andreas@gaisler.com>
96 lines
3.0 KiB
C
96 lines
3.0 KiB
C
/* Atomic operations. Sparc version.
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Copyright (C) 2019 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<https://www.gnu.org/licenses/>. */
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#ifndef _ATOMIC_MACHINE_H
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#define _ATOMIC_MACHINE_H 1
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#include <stdint.h>
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typedef int8_t atomic8_t;
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typedef uint8_t uatomic8_t;
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typedef int_fast8_t atomic_fast8_t;
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typedef uint_fast8_t uatomic_fast8_t;
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typedef int16_t atomic16_t;
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typedef uint16_t uatomic16_t;
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typedef int_fast16_t atomic_fast16_t;
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typedef uint_fast16_t uatomic_fast16_t;
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typedef int32_t atomic32_t;
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typedef uint32_t uatomic32_t;
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typedef int_fast32_t atomic_fast32_t;
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typedef uint_fast32_t uatomic_fast32_t;
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typedef int64_t atomic64_t;
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typedef uint64_t uatomic64_t;
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typedef int_fast64_t atomic_fast64_t;
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typedef uint_fast64_t uatomic_fast64_t;
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typedef intptr_t atomicptr_t;
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typedef uintptr_t uatomicptr_t;
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typedef intmax_t atomic_max_t;
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typedef uintmax_t uatomic_max_t;
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#ifdef __arch64__
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# define __HAVE_64B_ATOMICS 1
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#else
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# define __HAVE_64B_ATOMICS 0
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#endif
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#define USE_ATOMIC_COMPILER_BUILTINS 1
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/* XXX Is this actually correct? */
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#define ATOMIC_EXCHANGE_USES_CAS __HAVE_64B_ATOMICS
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/* Compare and exchange.
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For all "bool" routines, we return FALSE if exchange succesful. */
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#define __arch_compare_and_exchange_val_int(mem, newval, oldval, model) \
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({ \
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typeof (*mem) __oldval = (oldval); \
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__atomic_compare_exchange_n (mem, (void *) &__oldval, newval, 0, \
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model, __ATOMIC_RELAXED); \
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__oldval; \
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})
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#define atomic_compare_and_exchange_val_acq(mem, new, old) \
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({ \
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__typeof ((__typeof (*(mem))) *(mem)) __result; \
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if (sizeof (*mem) == 4 \
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|| (__HAVE_64B_ATOMICS && sizeof (*mem) == 8)) \
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__result = __arch_compare_and_exchange_val_int (mem, new, old, \
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__ATOMIC_ACQUIRE); \
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else \
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abort (); \
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__result; \
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})
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#ifdef __sparc_v9__
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# define atomic_full_barrier() \
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__asm __volatile ("membar #LoadLoad | #LoadStore" \
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" | #StoreLoad | #StoreStore" : : : "memory")
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# define atomic_read_barrier() \
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__asm __volatile ("membar #LoadLoad | #LoadStore" : : : "memory")
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# define atomic_write_barrier() \
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__asm __volatile ("membar #LoadStore | #StoreStore" : : : "memory")
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extern void __cpu_relax (void);
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# define atomic_spin_nop() __cpu_relax ()
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#endif
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#endif /* _ATOMIC_MACHINE_H */
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