glibc/sysdeps/aarch64/fpu/Versions
Joe Ramsay 3bb1af2051 aarch64: Add vector implementations of sin routines
Optimised implementations for single and double precision, Advanced
SIMD and SVE, copied from Arm Optimized Routines.

As previously, data tables are used via a barrier to prevent
overly aggressive constant inlining. Special-case handlers are
marked NOINLINE to avoid incurring the penalty of switching call
standards unnecessarily.

Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2023-06-30 09:04:16 +01:00

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libmvec {
GLIBC_2.38 {
_ZGVnN2v_cos;
_ZGVnN2v_sin;
_ZGVnN4v_cosf;
_ZGVnN4v_sinf;
_ZGVsMxv_cos;
_ZGVsMxv_cosf;
_ZGVsMxv_sin;
_ZGVsMxv_sinf;
}
}