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41bdb6e20c
2001-07-06 Paul Eggert <eggert@twinsun.com> * manual/argp.texi: Remove ignored LGPL copyright notice; it's not appropriate for documentation anyway. * manual/libc-texinfo.sh: "Library General Public License" -> "Lesser General Public License". 2001-07-06 Andreas Jaeger <aj@suse.de> * All files under GPL/LGPL version 2: Place under LGPL version 2.1.
879 lines
22 KiB
C
879 lines
22 KiB
C
/* Copyright (C) 1992, 1996-1999, 2000 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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Contributed by David Mosberger.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, write to the Free
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Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
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02111-1307 USA. */
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/* I/O access is restricted to ISA port space (ports 0..65535).
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Modern devices hopefully are sane enough not to put any performance
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critical registers in i/o space.
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On the first call to ioperm, the entire (E)ISA port space is mapped
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into the virtual address space at address io.base. mprotect calls
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are then used to enable/disable access to ports. Per page, there
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are PAGE_SIZE>>IO_SHIFT I/O ports (e.g., 256 ports on a Low Cost Alpha
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based system using 8KB pages).
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Keep in mind that this code should be able to run in a 32bit address
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space. It is therefore unreasonable to expect mmap'ing the entire
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sparse address space would work (e.g., the Low Cost Alpha chip has an
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I/O address space that's 512MB large!). */
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#include <errno.h>
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#include <fcntl.h>
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#include <stdio.h>
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#include <ctype.h>
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#include <stdlib.h>
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#include <string.h>
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#include <unistd.h>
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#include <sys/types.h>
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#include <sys/mman.h>
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#include <sys/io.h>
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#include <sysdep.h>
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#include <sys/syscall.h>
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#define PATH_ALPHA_SYSTYPE "/etc/alpha_systype"
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#define PATH_CPUINFO "/proc/cpuinfo"
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#define MAX_PORT 0x10000
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#define vip volatile int *
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#define vuip volatile unsigned int *
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#define vusp volatile unsigned short *
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#define vucp volatile unsigned char *
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#define JENSEN_IO_BASE (0x300000000UL)
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#define JENSEN_SPARSE_MEM (0x200000000UL)
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/* With respect to the I/O architecture, APECS and LCA are identical,
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so the following defines apply to LCA as well. */
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#define APECS_IO_BASE (0x1c0000000UL)
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#define APECS_SPARSE_MEM (0x200000000UL)
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#define APECS_DENSE_MEM (0x300000000UL)
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/* The same holds for CIA and PYXIS, except for PYXIS we prefer BWX. */
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#define CIA_IO_BASE (0x8580000000UL)
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#define CIA_SPARSE_MEM (0x8000000000UL)
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#define CIA_DENSE_MEM (0x8600000000UL)
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#define PYXIS_IO_BASE (0x8900000000UL)
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#define PYXIS_DENSE_MEM (0x8800000000UL)
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/* SABLE is EV4, GAMMA is EV5 */
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#define T2_IO_BASE (0x3a0000000UL)
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#define T2_SPARSE_MEM (0x200000000UL)
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#define T2_DENSE_MEM (0x3c0000000UL)
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#define GAMMA_IO_BASE (0x83a0000000UL)
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#define GAMMA_SPARSE_MEM (0x8200000000UL)
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#define GAMMA_DENSE_MEM (0x83c0000000UL)
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/* NOTE: these are hardwired to PCI bus 0 addresses!!! */
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#define MCPCIA_IO_BASE (0xf980000000UL)
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#define MCPCIA_SPARSE_MEM (0xf800000000UL)
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#define MCPCIA_DENSE_MEM (0xf900000000UL)
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/* Tsunami and Irongate use the same offsets, at least for hose 0. */
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#define TSUNAMI_IO_BASE (0x801fc000000UL)
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#define TSUNAMI_DENSE_MEM (0x80000000000UL)
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/* Polaris has SPARSE space, but we prefer to use only DENSE
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because of some idiosyncracies in actually using SPARSE. */
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#define POLARIS_IO_BASE (0xf9fc000000UL)
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#define POLARIS_DENSE_MEM (0xf900000000UL)
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typedef enum {
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IOSYS_UNKNOWN, IOSYS_JENSEN, IOSYS_APECS, IOSYS_CIA, IOSYS_PYXIS, IOSYS_T2,
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IOSYS_TSUNAMI, IOSYS_MCPCIA, IOSYS_GAMMA, IOSYS_POLARIS,
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IOSYS_CPUDEP, IOSYS_PCIDEP
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} iosys_t;
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typedef enum {
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IOSWIZZLE_JENSEN, IOSWIZZLE_SPARSE, IOSWIZZLE_DENSE
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} ioswizzle_t;
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static struct io_system {
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unsigned long int bus_memory_base;
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unsigned long int sparse_bus_mem_base;
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unsigned long int bus_io_base;
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} io_system[] = { /* NOTE! must match iosys_t enumeration */
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/* UNKNOWN */ {0, 0, 0},
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/* JENSEN */ {0, JENSEN_SPARSE_MEM, JENSEN_IO_BASE},
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/* APECS */ {APECS_DENSE_MEM, APECS_SPARSE_MEM, APECS_IO_BASE},
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/* CIA */ {CIA_DENSE_MEM, CIA_SPARSE_MEM, CIA_IO_BASE},
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/* PYXIS */ {PYXIS_DENSE_MEM, 0, PYXIS_IO_BASE},
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/* T2 */ {T2_DENSE_MEM, T2_SPARSE_MEM, T2_IO_BASE},
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/* TSUNAMI */ {TSUNAMI_DENSE_MEM, 0, TSUNAMI_IO_BASE},
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/* MCPCIA */ {MCPCIA_DENSE_MEM, MCPCIA_SPARSE_MEM, MCPCIA_IO_BASE},
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/* GAMMA */ {GAMMA_DENSE_MEM, GAMMA_SPARSE_MEM, GAMMA_IO_BASE},
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/* POLARIS */ {POLARIS_DENSE_MEM, 0, POLARIS_IO_BASE},
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/* CPUDEP */ {0, 0, 0}, /* for platforms dependent on CPU type */
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/* PCIDEP */ {0, 0, 0}, /* for platforms dependent on core logic */
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};
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static struct platform {
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const char *name;
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iosys_t io_sys;
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} platform[] = {
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{"Alcor", IOSYS_CIA},
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{"Avanti", IOSYS_APECS},
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{"Cabriolet", IOSYS_APECS},
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{"EB164", IOSYS_PCIDEP},
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{"EB64+", IOSYS_APECS},
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{"EB66", IOSYS_APECS},
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{"EB66P", IOSYS_APECS},
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{"Jensen", IOSYS_JENSEN},
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{"Miata", IOSYS_PYXIS},
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{"Mikasa", IOSYS_CPUDEP},
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{"Nautilus", IOSYS_TSUNAMI},
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{"Noname", IOSYS_APECS},
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{"Noritake", IOSYS_CPUDEP},
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{"Rawhide", IOSYS_MCPCIA},
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{"Ruffian", IOSYS_PYXIS},
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{"Sable", IOSYS_CPUDEP},
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{"Takara", IOSYS_CIA},
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{"Tsunami", IOSYS_TSUNAMI},
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{"XL", IOSYS_APECS},
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};
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struct ioswtch {
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void (*sethae)(unsigned long int addr);
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void (*outb)(unsigned char b, unsigned long int port);
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void (*outw)(unsigned short b, unsigned long int port);
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void (*outl)(unsigned int b, unsigned long int port);
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unsigned int (*inb)(unsigned long int port);
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unsigned int (*inw)(unsigned long int port);
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unsigned int (*inl)(unsigned long int port);
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};
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static struct {
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unsigned long int hae_cache;
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unsigned long int base;
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struct ioswtch * swp;
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unsigned long int bus_memory_base;
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unsigned long int sparse_bus_memory_base;
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unsigned long int io_base;
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ioswizzle_t swiz;
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} io;
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static inline void
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stb_mb(unsigned char val, unsigned long addr)
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{
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__asm__("stb %1,%0; mb" : "=m"(*(vucp)addr) : "r"(val));
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}
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static inline void
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stw_mb(unsigned short val, unsigned long addr)
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{
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__asm__("stw %1,%0; mb" : "=m"(*(vusp)addr) : "r"(val));
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}
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static inline void
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stl_mb(unsigned int val, unsigned long addr)
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{
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__asm__("stl %1,%0; mb" : "=m"(*(vip)addr) : "r"(val));
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}
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/* No need to examine error -- sethae never fails. */
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static inline void
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__sethae(unsigned long value)
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{
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register unsigned long r16 __asm__("$16") = value;
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register unsigned long r0 __asm__("$0") = __NR_sethae;
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__asm__ __volatile__ ("callsys"
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: "=r"(r0)
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: "0"(r0), "r" (r16)
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: inline_syscall_clobbers, "$19");
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}
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extern long __pciconfig_iobase(enum __pciconfig_iobase_which __which,
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unsigned long int __bus,
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unsigned long int __dfn);
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static inline unsigned long int
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port_to_cpu_addr (unsigned long int port, ioswizzle_t ioswiz, int size)
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{
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if (ioswiz == IOSWIZZLE_SPARSE)
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return io.base + (port << 5) + ((size - 1) << 3);
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else if (ioswiz == IOSWIZZLE_DENSE)
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return port + io.base;
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else
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return io.base + (port << 7) + ((size - 1) << 5);
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}
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static inline void
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inline_sethae (unsigned long int addr, ioswizzle_t ioswiz)
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{
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if (ioswiz == IOSWIZZLE_SPARSE)
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{
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unsigned long int msb;
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/* no need to set hae if msb is 0: */
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msb = addr & 0xf8000000;
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if (msb && msb != io.hae_cache)
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{
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io.hae_cache = msb;
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__sethae (msb);
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}
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}
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else if (ioswiz == IOSWIZZLE_JENSEN)
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{
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/* HAE on the Jensen is bits 31:25 shifted right. */
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addr >>= 25;
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if (addr != io.hae_cache)
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{
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io.hae_cache = addr;
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__sethae (addr);
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}
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}
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}
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static inline void
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inline_outb (unsigned char b, unsigned long int port, ioswizzle_t ioswiz)
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{
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unsigned int w;
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unsigned long int addr = port_to_cpu_addr (port, ioswiz, 1);
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asm ("insbl %2,%1,%0" : "=r" (w) : "ri" (port & 0x3), "r" (b));
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stl_mb(w, addr);
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}
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static inline void
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inline_outw (unsigned short int b, unsigned long int port, ioswizzle_t ioswiz)
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{
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unsigned long w;
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unsigned long int addr = port_to_cpu_addr (port, ioswiz, 2);
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asm ("inswl %2,%1,%0" : "=r" (w) : "ri" (port & 0x3), "r" (b));
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stl_mb(w, addr);
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}
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static inline void
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inline_outl (unsigned int b, unsigned long int port, ioswizzle_t ioswiz)
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{
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unsigned long int addr = port_to_cpu_addr (port, ioswiz, 4);
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stl_mb(b, addr);
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}
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static inline unsigned int
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inline_inb (unsigned long int port, ioswizzle_t ioswiz)
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{
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unsigned long int addr = port_to_cpu_addr (port, ioswiz, 1);
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int result;
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result = *(vip) addr;
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result >>= (port & 3) * 8;
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return 0xffUL & result;
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}
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static inline unsigned int
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inline_inw (unsigned long int port, ioswizzle_t ioswiz)
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{
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unsigned long int addr = port_to_cpu_addr (port, ioswiz, 2);
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int result;
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result = *(vip) addr;
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result >>= (port & 3) * 8;
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return 0xffffUL & result;
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}
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static inline unsigned int
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inline_inl (unsigned long int port, ioswizzle_t ioswiz)
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{
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unsigned long int addr = port_to_cpu_addr (port, ioswiz, 4);
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return *(vuip) addr;
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}
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/*
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* Now define the inline functions for CPUs supporting byte/word insns,
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* and whose core logic supports I/O space accesses utilizing them.
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*
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* These routines could be used by MIATA, for example, because it has
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* and EV56 plus PYXIS, but it currently uses SPARSE anyway. This is
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* also true of RX164 which used POLARIS, but we will choose to use
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* these routines in that case instead of SPARSE.
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*
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* These routines are necessary for TSUNAMI/TYPHOON based platforms,
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* which will have (at least) EV6.
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*/
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static inline unsigned long int
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dense_port_to_cpu_addr (unsigned long int port)
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{
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return port + io.base;
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}
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static inline void
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inline_bwx_outb (unsigned char b, unsigned long int port)
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{
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unsigned long int addr = dense_port_to_cpu_addr (port);
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stb_mb (b, addr);
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}
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static inline void
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inline_bwx_outw (unsigned short int b, unsigned long int port)
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{
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unsigned long int addr = dense_port_to_cpu_addr (port);
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stw_mb (b, addr);
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}
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static inline void
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inline_bwx_outl (unsigned int b, unsigned long int port)
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{
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unsigned long int addr = dense_port_to_cpu_addr (port);
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stl_mb (b, addr);
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}
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static inline unsigned int
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inline_bwx_inb (unsigned long int port)
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{
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unsigned long int addr = dense_port_to_cpu_addr (port);
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unsigned char r;
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__asm__ ("ldbu %0,%1" : "=r"(r) : "m"(*(vucp)addr));
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return r;
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}
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static inline unsigned int
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inline_bwx_inw (unsigned long int port)
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{
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unsigned long int addr = dense_port_to_cpu_addr (port);
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unsigned short r;
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__asm__ ("ldwu %0,%1" : "=r"(r) : "m"(*(vusp)addr));
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return r;
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}
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static inline unsigned int
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inline_bwx_inl (unsigned long int port)
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{
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unsigned long int addr = dense_port_to_cpu_addr (port);
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return *(vuip) addr;
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}
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/* macros to define routines with appropriate names and functions */
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/* these do either SPARSE or JENSEN swizzle */
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#define DCL_SETHAE(name, ioswiz) \
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static void \
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name##_sethae (unsigned long int addr) \
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{ \
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inline_sethae (addr, IOSWIZZLE_##ioswiz); \
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}
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#define DCL_OUT(name, func, type, ioswiz) \
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static void \
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name##_##func (unsigned type b, unsigned long int addr) \
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{ \
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inline_##func (b, addr, IOSWIZZLE_##ioswiz); \
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}
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#define DCL_IN(name, func, ioswiz) \
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static unsigned int \
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name##_##func (unsigned long int addr) \
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{ \
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return inline_##func (addr, IOSWIZZLE_##ioswiz); \
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}
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/* these do DENSE, so no swizzle is needed */
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#define DCL_OUT_BWX(name, func, type) \
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static void \
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name##_##func (unsigned type b, unsigned long int addr) \
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{ \
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inline_bwx_##func (b, addr); \
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}
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#define DCL_IN_BWX(name, func) \
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static unsigned int \
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name##_##func (unsigned long int addr) \
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{ \
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return inline_bwx_##func (addr); \
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}
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/* now declare/define the necessary routines */
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DCL_SETHAE(jensen, JENSEN)
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DCL_OUT(jensen, outb, char, JENSEN)
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DCL_OUT(jensen, outw, short int, JENSEN)
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DCL_OUT(jensen, outl, int, JENSEN)
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DCL_IN(jensen, inb, JENSEN)
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DCL_IN(jensen, inw, JENSEN)
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DCL_IN(jensen, inl, JENSEN)
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DCL_SETHAE(sparse, SPARSE)
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DCL_OUT(sparse, outb, char, SPARSE)
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DCL_OUT(sparse, outw, short int, SPARSE)
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DCL_OUT(sparse, outl, int, SPARSE)
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DCL_IN(sparse, inb, SPARSE)
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DCL_IN(sparse, inw, SPARSE)
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DCL_IN(sparse, inl, SPARSE)
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DCL_SETHAE(dense, DENSE)
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DCL_OUT_BWX(dense, outb, char)
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DCL_OUT_BWX(dense, outw, short int)
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DCL_OUT_BWX(dense, outl, int)
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DCL_IN_BWX(dense, inb)
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DCL_IN_BWX(dense, inw)
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DCL_IN_BWX(dense, inl)
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/* define the "swizzle" switch */
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static struct ioswtch ioswtch[] = {
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{
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jensen_sethae,
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jensen_outb, jensen_outw, jensen_outl,
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jensen_inb, jensen_inw, jensen_inl
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},
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{
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sparse_sethae,
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sparse_outb, sparse_outw, sparse_outl,
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sparse_inb, sparse_inw, sparse_inl
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},
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{
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dense_sethae,
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dense_outb, dense_outw, dense_outl,
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dense_inb, dense_inw, dense_inl
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}
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};
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#undef DEBUG_IOPERM
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/* Routine to process the /proc/cpuinfo information into the fields
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that are required for correctly determining the platform parameters. */
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struct cpuinfo_data
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{
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char systype[256]; /* system type field */
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char sysvari[256]; /* system variation field */
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char cpumodel[256]; /* cpu model field */
|
|
};
|
|
|
|
static inline int
|
|
process_cpuinfo(struct cpuinfo_data *data)
|
|
{
|
|
int got_type, got_vari, got_model;
|
|
char dummy[256];
|
|
FILE * fp;
|
|
int n;
|
|
|
|
data->systype[0] = 0;
|
|
data->sysvari[0] = 0;
|
|
data->cpumodel[0] = 0;
|
|
|
|
/* If there's an /etc/alpha_systype link, we're intending to override
|
|
whatever's in /proc/cpuinfo. */
|
|
n = __readlink (PATH_ALPHA_SYSTYPE, data->systype, 256 - 1);
|
|
if (n > 0)
|
|
{
|
|
data->systype[n] = '\0';
|
|
return 1;
|
|
}
|
|
|
|
fp = fopen (PATH_CPUINFO, "r");
|
|
if (!fp)
|
|
return 0;
|
|
|
|
got_type = got_vari = got_model = 0;
|
|
|
|
while (1)
|
|
{
|
|
if (fgets (dummy, 256, fp) == NULL)
|
|
break;
|
|
if (!got_type &&
|
|
sscanf (dummy, "system type : %256[^\n]\n", data->systype) == 1)
|
|
got_type = 1;
|
|
if (!got_vari &&
|
|
sscanf (dummy, "system variation : %256[^\n]\n", data->sysvari) == 1)
|
|
got_vari = 1;
|
|
if (!got_model &&
|
|
sscanf (dummy, "cpu model : %256[^\n]\n", data->cpumodel) == 1)
|
|
got_model = 1;
|
|
}
|
|
|
|
fclose (fp);
|
|
|
|
#ifdef DEBUG_IOPERM
|
|
fprintf(stderr, "system type: `%s'\n", data->systype);
|
|
fprintf(stderr, "system vari: `%s'\n", data->sysvari);
|
|
fprintf(stderr, "cpu model: `%s'\n", data->cpumodel);
|
|
#endif
|
|
|
|
return got_type + got_vari + got_model;
|
|
}
|
|
|
|
|
|
/*
|
|
* Initialize I/O system.
|
|
*/
|
|
static int
|
|
init_iosys (void)
|
|
{
|
|
long addr;
|
|
int i, olderrno = errno;
|
|
struct cpuinfo_data data;
|
|
|
|
/* First try the pciconfig_iobase syscall added to 2.2.15 and 2.3.99. */
|
|
|
|
#ifdef __NR_pciconfig_iobase
|
|
addr = __pciconfig_iobase (IOBASE_DENSE_MEM, 0, 0);
|
|
if (addr != -1)
|
|
{
|
|
ioswizzle_t io_swiz;
|
|
|
|
if (addr == 0)
|
|
{
|
|
/* Only Jensen doesn't have dense mem space. */
|
|
io.sparse_bus_memory_base
|
|
= io_system[IOSYS_JENSEN].sparse_bus_mem_base;
|
|
io.io_base = io_system[IOSYS_JENSEN].bus_io_base;
|
|
io_swiz = IOSWIZZLE_JENSEN;
|
|
}
|
|
else
|
|
{
|
|
io.bus_memory_base = addr;
|
|
|
|
addr = __pciconfig_iobase (IOBASE_DENSE_IO, 0, 0);
|
|
if (addr != 0)
|
|
{
|
|
/* The X server uses _bus_base_sparse == 0 to know that
|
|
BWX access are supported to dense mem space. This is
|
|
true of every system that supports dense io space, so
|
|
never fill in io.sparse_bus_memory_base in this case. */
|
|
io_swiz = IOSWIZZLE_DENSE;
|
|
io.io_base = addr;
|
|
}
|
|
else
|
|
{
|
|
io.sparse_bus_memory_base
|
|
= __pciconfig_iobase (IOBASE_SPARSE_MEM, 0, 0);
|
|
io.io_base = __pciconfig_iobase (IOBASE_SPARSE_IO, 0, 0);
|
|
io_swiz = IOSWIZZLE_SPARSE;
|
|
}
|
|
}
|
|
|
|
io.swiz = io_swiz;
|
|
io.swp = &ioswtch[io_swiz];
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
/* Second, collect the contents of /etc/alpha_systype or /proc/cpuinfo. */
|
|
|
|
if (process_cpuinfo(&data) == 0)
|
|
{
|
|
/* This can happen if the format of /proc/cpuinfo changes. */
|
|
fprintf (stderr,
|
|
"ioperm.init_iosys: Unable to determine system type.\n"
|
|
"\t(May need " PATH_ALPHA_SYSTYPE " symlink?)\n");
|
|
__set_errno (ENODEV);
|
|
return -1;
|
|
}
|
|
|
|
/* Translate systype name into i/o system. */
|
|
for (i = 0; i < sizeof (platform) / sizeof (platform[0]); ++i)
|
|
{
|
|
if (strcmp (platform[i].name, data.systype) == 0)
|
|
{
|
|
iosys_t io_sys = platform[i].io_sys;
|
|
|
|
/* Some platforms can have either EV4 or EV5 CPUs. */
|
|
if (io_sys == IOSYS_CPUDEP)
|
|
{
|
|
/* SABLE or MIKASA or NORITAKE so far. */
|
|
if (strcmp (platform[i].name, "Sable") == 0)
|
|
{
|
|
if (strncmp (data.cpumodel, "EV4", 3) == 0)
|
|
io_sys = IOSYS_T2;
|
|
else if (strncmp (data.cpumodel, "EV5", 3) == 0)
|
|
io_sys = IOSYS_GAMMA;
|
|
}
|
|
else
|
|
{
|
|
/* This covers MIKASA/NORITAKE. */
|
|
if (strncmp (data.cpumodel, "EV4", 3) == 0)
|
|
io_sys = IOSYS_APECS;
|
|
else if (strncmp (data.cpumodel, "EV5", 3) == 0)
|
|
io_sys = IOSYS_CIA;
|
|
}
|
|
if (io_sys == IOSYS_CPUDEP)
|
|
{
|
|
/* This can happen if the format of /proc/cpuinfo changes.*/
|
|
fprintf (stderr, "ioperm.init_iosys: Unable to determine"
|
|
" CPU model.\n");
|
|
__set_errno (ENODEV);
|
|
return -1;
|
|
}
|
|
}
|
|
/* Some platforms can have different core logic chipsets */
|
|
if (io_sys == IOSYS_PCIDEP)
|
|
{
|
|
/* EB164 so far */
|
|
if (strcmp (data.systype, "EB164") == 0)
|
|
{
|
|
if (strncmp (data.sysvari, "RX164", 5) == 0)
|
|
io_sys = IOSYS_POLARIS;
|
|
else if (strncmp (data.sysvari, "LX164", 5) == 0
|
|
|| strncmp (data.sysvari, "SX164", 5) == 0)
|
|
io_sys = IOSYS_PYXIS;
|
|
else
|
|
io_sys = IOSYS_CIA;
|
|
}
|
|
if (io_sys == IOSYS_PCIDEP)
|
|
{
|
|
/* This can happen if the format of /proc/cpuinfo changes.*/
|
|
fprintf (stderr, "ioperm.init_iosys: Unable to determine"
|
|
" core logic chipset.\n");
|
|
__set_errno (ENODEV);
|
|
return -1;
|
|
}
|
|
}
|
|
io.bus_memory_base = io_system[io_sys].bus_memory_base;
|
|
io.sparse_bus_memory_base = io_system[io_sys].sparse_bus_mem_base;
|
|
io.io_base = io_system[io_sys].bus_io_base;
|
|
|
|
if (io_sys == IOSYS_JENSEN)
|
|
io.swiz = IOSWIZZLE_JENSEN;
|
|
else if (io_sys == IOSYS_TSUNAMI
|
|
|| io_sys == IOSYS_POLARIS
|
|
|| io_sys == IOSYS_PYXIS)
|
|
io.swiz = IOSWIZZLE_DENSE;
|
|
else
|
|
io.swiz = IOSWIZZLE_SPARSE;
|
|
io.swp = &ioswtch[io.swiz];
|
|
|
|
__set_errno (olderrno);
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
__set_errno (ENODEV);
|
|
fprintf(stderr, "ioperm.init_iosys: Platform not recognized.\n"
|
|
"\t(May need " PATH_ALPHA_SYSTYPE " symlink?)\n");
|
|
return -1;
|
|
}
|
|
|
|
|
|
int
|
|
_ioperm (unsigned long int from, unsigned long int num, int turn_on)
|
|
{
|
|
unsigned long int addr, len, pagesize = __getpagesize();
|
|
int prot;
|
|
|
|
if (!io.swp && init_iosys() < 0)
|
|
{
|
|
#ifdef DEBUG_IOPERM
|
|
fprintf(stderr, "ioperm: init_iosys() failed (%m)\n");
|
|
#endif
|
|
return -1;
|
|
}
|
|
|
|
/* This test isn't as silly as it may look like; consider overflows! */
|
|
if (from >= MAX_PORT || from + num > MAX_PORT)
|
|
{
|
|
__set_errno (EINVAL);
|
|
#ifdef DEBUG_IOPERM
|
|
fprintf(stderr, "ioperm: from/num out of range\n");
|
|
#endif
|
|
return -1;
|
|
}
|
|
|
|
#ifdef DEBUG_IOPERM
|
|
fprintf(stderr, "ioperm: turn_on %d io.base %ld\n", turn_on, io.base);
|
|
#endif
|
|
|
|
if (turn_on)
|
|
{
|
|
if (!io.base)
|
|
{
|
|
int fd;
|
|
|
|
io.hae_cache = 0;
|
|
if (io.swiz != IOSWIZZLE_DENSE)
|
|
{
|
|
/* Synchronize with hw. */
|
|
__sethae (0);
|
|
}
|
|
|
|
fd = __open ("/dev/mem", O_RDWR);
|
|
if (fd < 0)
|
|
{
|
|
#ifdef DEBUG_IOPERM
|
|
fprintf(stderr, "ioperm: /dev/mem open failed (%m)\n");
|
|
#endif
|
|
return -1;
|
|
}
|
|
|
|
addr = port_to_cpu_addr (0, io.swiz, 1);
|
|
len = port_to_cpu_addr (MAX_PORT, io.swiz, 1) - addr;
|
|
io.base =
|
|
(unsigned long int) __mmap (0, len, PROT_NONE, MAP_SHARED,
|
|
fd, io.io_base);
|
|
__close (fd);
|
|
#ifdef DEBUG_IOPERM
|
|
fprintf(stderr, "ioperm: mmap of len 0x%lx returned 0x%lx\n",
|
|
len, io.base);
|
|
#endif
|
|
if ((long) io.base == -1)
|
|
return -1;
|
|
}
|
|
prot = PROT_READ | PROT_WRITE;
|
|
}
|
|
else
|
|
{
|
|
if (!io.base)
|
|
return 0; /* never was turned on... */
|
|
|
|
/* turnoff access to relevant pages: */
|
|
prot = PROT_NONE;
|
|
}
|
|
addr = port_to_cpu_addr (from, io.swiz, 1);
|
|
addr &= ~(pagesize - 1);
|
|
len = port_to_cpu_addr (from + num, io.swiz, 1) - addr;
|
|
return __mprotect ((void *) addr, len, prot);
|
|
}
|
|
|
|
|
|
int
|
|
_iopl (int level)
|
|
{
|
|
switch (level)
|
|
{
|
|
case 0:
|
|
return 0;
|
|
|
|
case 1: case 2: case 3:
|
|
return _ioperm (0, MAX_PORT, 1);
|
|
|
|
default:
|
|
__set_errno (EINVAL);
|
|
return -1;
|
|
}
|
|
}
|
|
|
|
|
|
void
|
|
_sethae (unsigned long int addr)
|
|
{
|
|
if (!io.swp && init_iosys () < 0)
|
|
return;
|
|
|
|
io.swp->sethae (addr);
|
|
}
|
|
|
|
|
|
void
|
|
_outb (unsigned char b, unsigned long int port)
|
|
{
|
|
if (port >= MAX_PORT)
|
|
return;
|
|
|
|
io.swp->outb (b, port);
|
|
}
|
|
|
|
|
|
void
|
|
_outw (unsigned short b, unsigned long int port)
|
|
{
|
|
if (port >= MAX_PORT)
|
|
return;
|
|
|
|
io.swp->outw (b, port);
|
|
}
|
|
|
|
|
|
void
|
|
_outl (unsigned int b, unsigned long int port)
|
|
{
|
|
if (port >= MAX_PORT)
|
|
return;
|
|
|
|
io.swp->outl (b, port);
|
|
}
|
|
|
|
|
|
unsigned int
|
|
_inb (unsigned long int port)
|
|
{
|
|
return io.swp->inb (port);
|
|
}
|
|
|
|
|
|
unsigned int
|
|
_inw (unsigned long int port)
|
|
{
|
|
return io.swp->inw (port);
|
|
}
|
|
|
|
|
|
unsigned int
|
|
_inl (unsigned long int port)
|
|
{
|
|
return io.swp->inl (port);
|
|
}
|
|
|
|
|
|
unsigned long int
|
|
_bus_base(void)
|
|
{
|
|
if (!io.swp && init_iosys () < 0)
|
|
return -1;
|
|
return io.bus_memory_base;
|
|
}
|
|
|
|
unsigned long int
|
|
_bus_base_sparse(void)
|
|
{
|
|
if (!io.swp && init_iosys () < 0)
|
|
return -1;
|
|
return io.sparse_bus_memory_base;
|
|
}
|
|
|
|
int
|
|
_hae_shift(void)
|
|
{
|
|
if (!io.swp && init_iosys () < 0)
|
|
return -1;
|
|
if (io.swiz == IOSWIZZLE_JENSEN)
|
|
return 7;
|
|
if (io.swiz == IOSWIZZLE_SPARSE)
|
|
return 5;
|
|
return 0;
|
|
}
|
|
|
|
weak_alias (_sethae, sethae);
|
|
weak_alias (_ioperm, ioperm);
|
|
weak_alias (_iopl, iopl);
|
|
weak_alias (_inb, inb);
|
|
weak_alias (_inw, inw);
|
|
weak_alias (_inl, inl);
|
|
weak_alias (_outb, outb);
|
|
weak_alias (_outw, outw);
|
|
weak_alias (_outl, outl);
|
|
weak_alias (_bus_base, bus_base);
|
|
weak_alias (_bus_base_sparse, bus_base_sparse);
|
|
weak_alias (_hae_shift, hae_shift);
|