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ae308947ff
1. Refactor files so that all implementations are in the multiarch
directory
- Moved the implementation portion of memcmp sse2 from memcmp.S to
multiarch/memcmp-sse2.S
- The non-multiarch file now only includes one of the
implementations in the multiarch directory based on the compiled
ISA level (only used for non-multiarch builds. Otherwise we go
through the ifunc selector).
2. Add ISA level build guards to different implementations.
- I.e memcmp-avx2-movsb.S which is ISA level 3 will only build if
compiled ISA level <= 3. Otherwise there is no reason to include
it as we will always use one of the ISA level 4
implementations (memcmp-evex-movbe.S).
3. Add new multiarch/rtld-{w}memcmp{eq}.S that just include the
non-multiarch {w}memcmp{eq}.S which will in turn select the best
implementation based on the compiled ISA level.
4. Refactor the ifunc selector and ifunc implementation list to use
the ISA level aware wrapper macros that allow functions below the
compiled ISA level (with a guranteed replacement) to be skipped.
Tested with and without multiarch on x86_64 for ISA levels:
{generic, x86-64-v2, x86-64-v3, x86-64-v4}
And m32 with and without multiarch.
242 lines
6.5 KiB
ArmAsm
242 lines
6.5 KiB
ArmAsm
/* __memcmpeq optimized with EVEX.
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Copyright (C) 2017-2022 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<https://www.gnu.org/licenses/>. */
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#include <isa-level.h>
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#if ISA_SHOULD_BUILD (4)
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/* __memcmpeq is implemented as:
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1. Use ymm vector compares when possible. The only case where
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vector compares is not possible for when size < VEC_SIZE
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and loading from either s1 or s2 would cause a page cross.
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2. Use xmm vector compare when size >= 8 bytes.
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3. Optimistically compare up to first 4 * VEC_SIZE one at a
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to check for early mismatches. Only do this if its guranteed the
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work is not wasted.
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4. If size is 8 * VEC_SIZE or less, unroll the loop.
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5. Compare 4 * VEC_SIZE at a time with the aligned first memory
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area.
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6. Use 2 vector compares when size is 2 * VEC_SIZE or less.
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7. Use 4 vector compares when size is 4 * VEC_SIZE or less.
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8. Use 8 vector compares when size is 8 * VEC_SIZE or less. */
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# include <sysdep.h>
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# ifndef MEMCMPEQ
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# define MEMCMPEQ __memcmpeq_evex
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# endif
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# define VMOVU_MASK vmovdqu8
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# define VMOVU vmovdqu64
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# define VPCMP vpcmpub
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# define VPTEST vptestmb
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# define VEC_SIZE 32
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# define PAGE_SIZE 4096
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# define YMM0 ymm16
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# define YMM1 ymm17
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# define YMM2 ymm18
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# define YMM3 ymm19
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# define YMM4 ymm20
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# define YMM5 ymm21
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# define YMM6 ymm22
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.section .text.evex, "ax", @progbits
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ENTRY_P2ALIGN (MEMCMPEQ, 6)
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# ifdef __ILP32__
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/* Clear the upper 32 bits. */
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movl %edx, %edx
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# endif
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cmp $VEC_SIZE, %RDX_LP
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/* Fall through for [0, VEC_SIZE] as its the hottest. */
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ja L(more_1x_vec)
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/* Create mask of bytes that are guranteed to be valid because
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of length (edx). Using masked movs allows us to skip checks for
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page crosses/zero size. */
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movl $-1, %ecx
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bzhil %edx, %ecx, %ecx
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kmovd %ecx, %k2
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/* Use masked loads as VEC_SIZE could page cross where length
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(edx) would not. */
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VMOVU_MASK (%rsi), %YMM2{%k2}
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VPCMP $4,(%rdi), %YMM2, %k1{%k2}
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kmovd %k1, %eax
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ret
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L(last_1x_vec):
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VMOVU -(VEC_SIZE * 1)(%rsi, %rdx), %YMM1
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VPCMP $4, -(VEC_SIZE * 1)(%rdi, %rdx), %YMM1, %k1
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kmovd %k1, %eax
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L(return_neq0):
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ret
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.p2align 4
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L(more_1x_vec):
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/* From VEC + 1 to 2 * VEC. */
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VMOVU (%rsi), %YMM1
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/* Use compare not equals to directly check for mismatch. */
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VPCMP $4,(%rdi), %YMM1, %k1
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kmovd %k1, %eax
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testl %eax, %eax
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jnz L(return_neq0)
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cmpq $(VEC_SIZE * 2), %rdx
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jbe L(last_1x_vec)
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/* Check second VEC no matter what. */
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VMOVU VEC_SIZE(%rsi), %YMM2
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VPCMP $4, VEC_SIZE(%rdi), %YMM2, %k1
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kmovd %k1, %eax
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testl %eax, %eax
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jnz L(return_neq0)
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/* Less than 4 * VEC. */
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cmpq $(VEC_SIZE * 4), %rdx
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jbe L(last_2x_vec)
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/* Check third and fourth VEC no matter what. */
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VMOVU (VEC_SIZE * 2)(%rsi), %YMM3
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VPCMP $4,(VEC_SIZE * 2)(%rdi), %YMM3, %k1
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kmovd %k1, %eax
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testl %eax, %eax
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jnz L(return_neq0)
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VMOVU (VEC_SIZE * 3)(%rsi), %YMM4
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VPCMP $4,(VEC_SIZE * 3)(%rdi), %YMM4, %k1
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kmovd %k1, %eax
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testl %eax, %eax
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jnz L(return_neq0)
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/* Go to 4x VEC loop. */
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cmpq $(VEC_SIZE * 8), %rdx
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ja L(more_8x_vec)
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/* Handle remainder of size = 4 * VEC + 1 to 8 * VEC without any
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branches. */
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VMOVU -(VEC_SIZE * 4)(%rsi, %rdx), %YMM1
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VMOVU -(VEC_SIZE * 3)(%rsi, %rdx), %YMM2
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addq %rdx, %rdi
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/* Wait to load from s1 until addressed adjust due to
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unlamination. */
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/* vpxor will be all 0s if s1 and s2 are equal. Otherwise it
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will have some 1s. */
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vpxorq -(VEC_SIZE * 4)(%rdi), %YMM1, %YMM1
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/* Ternary logic to xor -(VEC_SIZE * 3)(%rdi) with YMM2 while
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oring with YMM1. Result is stored in YMM1. */
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vpternlogd $0xde, -(VEC_SIZE * 3)(%rdi), %YMM1, %YMM2
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VMOVU -(VEC_SIZE * 2)(%rsi, %rdx), %YMM3
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vpxorq -(VEC_SIZE * 2)(%rdi), %YMM3, %YMM3
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/* Or together YMM1, YMM2, and YMM3 into YMM3. */
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VMOVU -(VEC_SIZE)(%rsi, %rdx), %YMM4
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vpxorq -(VEC_SIZE)(%rdi), %YMM4, %YMM4
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/* Or together YMM2, YMM3, and YMM4 into YMM4. */
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vpternlogd $0xfe, %YMM2, %YMM3, %YMM4
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/* Compare YMM4 with 0. If any 1s s1 and s2 don't match. */
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VPTEST %YMM4, %YMM4, %k1
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kmovd %k1, %eax
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ret
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.p2align 4
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L(more_8x_vec):
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/* Set end of s1 in rdx. */
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leaq -(VEC_SIZE * 4)(%rdi, %rdx), %rdx
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/* rsi stores s2 - s1. This allows loop to only update one
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pointer. */
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subq %rdi, %rsi
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/* Align s1 pointer. */
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andq $-VEC_SIZE, %rdi
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/* Adjust because first 4x vec where check already. */
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subq $-(VEC_SIZE * 4), %rdi
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.p2align 4
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L(loop_4x_vec):
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VMOVU (%rsi, %rdi), %YMM1
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vpxorq (%rdi), %YMM1, %YMM1
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VMOVU VEC_SIZE(%rsi, %rdi), %YMM2
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vpternlogd $0xde,(VEC_SIZE)(%rdi), %YMM1, %YMM2
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VMOVU (VEC_SIZE * 2)(%rsi, %rdi), %YMM3
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vpxorq (VEC_SIZE * 2)(%rdi), %YMM3, %YMM3
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VMOVU (VEC_SIZE * 3)(%rsi, %rdi), %YMM4
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vpxorq (VEC_SIZE * 3)(%rdi), %YMM4, %YMM4
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vpternlogd $0xfe, %YMM2, %YMM3, %YMM4
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VPTEST %YMM4, %YMM4, %k1
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kmovd %k1, %eax
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testl %eax, %eax
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jnz L(return_neq2)
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subq $-(VEC_SIZE * 4), %rdi
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cmpq %rdx, %rdi
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jb L(loop_4x_vec)
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subq %rdx, %rdi
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VMOVU (VEC_SIZE * 3)(%rsi, %rdx), %YMM4
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vpxorq (VEC_SIZE * 3)(%rdx), %YMM4, %YMM4
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/* rdi has 4 * VEC_SIZE - remaining length. */
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cmpl $(VEC_SIZE * 3), %edi
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jae L(8x_last_1x_vec)
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/* Load regardless of branch. */
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VMOVU (VEC_SIZE * 2)(%rsi, %rdx), %YMM3
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/* Ternary logic to xor (VEC_SIZE * 2)(%rdx) with YMM3 while
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oring with YMM4. Result is stored in YMM4. */
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vpternlogd $0xf6,(VEC_SIZE * 2)(%rdx), %YMM3, %YMM4
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cmpl $(VEC_SIZE * 2), %edi
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jae L(8x_last_2x_vec)
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VMOVU VEC_SIZE(%rsi, %rdx), %YMM2
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vpxorq VEC_SIZE(%rdx), %YMM2, %YMM2
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VMOVU (%rsi, %rdx), %YMM1
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vpxorq (%rdx), %YMM1, %YMM1
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vpternlogd $0xfe, %YMM1, %YMM2, %YMM4
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L(8x_last_1x_vec):
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L(8x_last_2x_vec):
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VPTEST %YMM4, %YMM4, %k1
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kmovd %k1, %eax
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L(return_neq2):
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ret
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.p2align 4,, 8
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L(last_2x_vec):
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VMOVU -(VEC_SIZE * 2)(%rsi, %rdx), %YMM1
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vpxorq -(VEC_SIZE * 2)(%rdi, %rdx), %YMM1, %YMM1
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VMOVU -(VEC_SIZE * 1)(%rsi, %rdx), %YMM2
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vpternlogd $0xde, -(VEC_SIZE * 1)(%rdi, %rdx), %YMM1, %YMM2
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VPTEST %YMM2, %YMM2, %k1
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kmovd %k1, %eax
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ret
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/* 1 Bytes from next cache line. */
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END (MEMCMPEQ)
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#endif
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