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546 lines
20 KiB
C
546 lines
20 KiB
C
/* Copyright (C) 2002-2018 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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Contributed by Ulrich Drepper <drepper@redhat.com>, 2002.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<http://www.gnu.org/licenses/>. */
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#include <stdint.h>
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#include <tls.h> /* For tcbhead_t. */
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typedef int8_t atomic8_t;
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typedef uint8_t uatomic8_t;
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typedef int_fast8_t atomic_fast8_t;
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typedef uint_fast8_t uatomic_fast8_t;
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typedef int16_t atomic16_t;
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typedef uint16_t uatomic16_t;
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typedef int_fast16_t atomic_fast16_t;
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typedef uint_fast16_t uatomic_fast16_t;
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typedef int32_t atomic32_t;
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typedef uint32_t uatomic32_t;
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typedef int_fast32_t atomic_fast32_t;
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typedef uint_fast32_t uatomic_fast32_t;
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typedef int64_t atomic64_t;
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typedef uint64_t uatomic64_t;
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typedef int_fast64_t atomic_fast64_t;
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typedef uint_fast64_t uatomic_fast64_t;
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typedef intptr_t atomicptr_t;
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typedef uintptr_t uatomicptr_t;
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typedef intmax_t atomic_max_t;
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typedef uintmax_t uatomic_max_t;
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#ifndef LOCK_PREFIX
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# ifdef UP
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# define LOCK_PREFIX /* nothing */
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# else
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# define LOCK_PREFIX "lock;"
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# endif
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#endif
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#define __HAVE_64B_ATOMICS 0
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#define USE_ATOMIC_COMPILER_BUILTINS 0
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#define ATOMIC_EXCHANGE_USES_CAS 0
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#define atomic_compare_and_exchange_val_acq(mem, newval, oldval) \
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__sync_val_compare_and_swap (mem, oldval, newval)
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#define atomic_compare_and_exchange_bool_acq(mem, newval, oldval) \
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(! __sync_bool_compare_and_swap (mem, oldval, newval))
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#define __arch_c_compare_and_exchange_val_8_acq(mem, newval, oldval) \
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({ __typeof (*mem) ret; \
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__asm __volatile ("cmpl $0, %%gs:%P5\n\t" \
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"je 0f\n\t" \
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"lock\n" \
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"0:\tcmpxchgb %b2, %1" \
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: "=a" (ret), "=m" (*mem) \
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: "q" (newval), "m" (*mem), "0" (oldval), \
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"i" (offsetof (tcbhead_t, multiple_threads))); \
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ret; })
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#define __arch_c_compare_and_exchange_val_16_acq(mem, newval, oldval) \
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({ __typeof (*mem) ret; \
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__asm __volatile ("cmpl $0, %%gs:%P5\n\t" \
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"je 0f\n\t" \
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"lock\n" \
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"0:\tcmpxchgw %w2, %1" \
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: "=a" (ret), "=m" (*mem) \
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: "r" (newval), "m" (*mem), "0" (oldval), \
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"i" (offsetof (tcbhead_t, multiple_threads))); \
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ret; })
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#define __arch_c_compare_and_exchange_val_32_acq(mem, newval, oldval) \
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({ __typeof (*mem) ret; \
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__asm __volatile ("cmpl $0, %%gs:%P5\n\t" \
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"je 0f\n\t" \
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"lock\n" \
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"0:\tcmpxchgl %2, %1" \
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: "=a" (ret), "=m" (*mem) \
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: "r" (newval), "m" (*mem), "0" (oldval), \
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"i" (offsetof (tcbhead_t, multiple_threads))); \
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ret; })
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/* XXX We do not really need 64-bit compare-and-exchange. At least
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not in the moment. Using it would mean causing portability
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problems since not many other 32-bit architectures have support for
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such an operation. So don't define any code for now. If it is
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really going to be used the code below can be used on Intel Pentium
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and later, but NOT on i486. */
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#if 1
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# define __arch_compare_and_exchange_val_64_acq(mem, newval, oldval) \
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({ __typeof (*mem) ret = *(mem); \
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abort (); \
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ret = (newval); \
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ret = (oldval); \
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ret; })
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# define __arch_c_compare_and_exchange_val_64_acq(mem, newval, oldval) \
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({ __typeof (*mem) ret = *(mem); \
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abort (); \
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ret = (newval); \
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ret = (oldval); \
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ret; })
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#else
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# ifdef __PIC__
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# define __arch_compare_and_exchange_val_64_acq(mem, newval, oldval) \
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({ __typeof (*mem) ret; \
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__asm __volatile ("xchgl %2, %%ebx\n\t" \
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LOCK_PREFIX "cmpxchg8b %1\n\t" \
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"xchgl %2, %%ebx" \
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: "=A" (ret), "=m" (*mem) \
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: "DS" (((unsigned long long int) (newval)) \
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& 0xffffffff), \
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"c" (((unsigned long long int) (newval)) >> 32), \
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"m" (*mem), "a" (((unsigned long long int) (oldval)) \
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& 0xffffffff), \
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"d" (((unsigned long long int) (oldval)) >> 32)); \
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ret; })
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# define __arch_c_compare_and_exchange_val_64_acq(mem, newval, oldval) \
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({ __typeof (*mem) ret; \
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__asm __volatile ("xchgl %2, %%ebx\n\t" \
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"cmpl $0, %%gs:%P7\n\t" \
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"je 0f\n\t" \
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"lock\n" \
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"0:\tcmpxchg8b %1\n\t" \
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"xchgl %2, %%ebx" \
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: "=A" (ret), "=m" (*mem) \
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: "DS" (((unsigned long long int) (newval)) \
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& 0xffffffff), \
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"c" (((unsigned long long int) (newval)) >> 32), \
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"m" (*mem), "a" (((unsigned long long int) (oldval)) \
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& 0xffffffff), \
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"d" (((unsigned long long int) (oldval)) >> 32), \
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"i" (offsetof (tcbhead_t, multiple_threads))); \
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ret; })
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# else
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# define __arch_compare_and_exchange_val_64_acq(mem, newval, oldval) \
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({ __typeof (*mem) ret; \
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__asm __volatile (LOCK_PREFIX "cmpxchg8b %1" \
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: "=A" (ret), "=m" (*mem) \
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: "b" (((unsigned long long int) (newval)) \
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& 0xffffffff), \
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"c" (((unsigned long long int) (newval)) >> 32), \
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"m" (*mem), "a" (((unsigned long long int) (oldval)) \
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& 0xffffffff), \
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"d" (((unsigned long long int) (oldval)) >> 32)); \
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ret; })
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# define __arch_c_compare_and_exchange_val_64_acq(mem, newval, oldval) \
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({ __typeof (*mem) ret; \
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__asm __volatile ("cmpl $0, %%gs:%P7\n\t" \
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"je 0f\n\t" \
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"lock\n" \
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"0:\tcmpxchg8b %1" \
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: "=A" (ret), "=m" (*mem) \
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: "b" (((unsigned long long int) (newval)) \
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& 0xffffffff), \
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"c" (((unsigned long long int) (newval)) >> 32), \
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"m" (*mem), "a" (((unsigned long long int) (oldval)) \
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& 0xffffffff), \
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"d" (((unsigned long long int) (oldval)) >> 32), \
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"i" (offsetof (tcbhead_t, multiple_threads))); \
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ret; })
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# endif
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#endif
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/* Note that we need no lock prefix. */
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#define atomic_exchange_acq(mem, newvalue) \
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({ __typeof (*mem) result; \
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if (sizeof (*mem) == 1) \
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__asm __volatile ("xchgb %b0, %1" \
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: "=q" (result), "=m" (*mem) \
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: "0" (newvalue), "m" (*mem)); \
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else if (sizeof (*mem) == 2) \
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__asm __volatile ("xchgw %w0, %1" \
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: "=r" (result), "=m" (*mem) \
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: "0" (newvalue), "m" (*mem)); \
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else if (sizeof (*mem) == 4) \
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__asm __volatile ("xchgl %0, %1" \
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: "=r" (result), "=m" (*mem) \
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: "0" (newvalue), "m" (*mem)); \
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else \
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{ \
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result = 0; \
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abort (); \
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} \
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result; })
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#define __arch_exchange_and_add_body(lock, pfx, mem, value) \
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({ __typeof (*mem) __result; \
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__typeof (value) __addval = (value); \
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if (sizeof (*mem) == 1) \
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__asm __volatile (lock "xaddb %b0, %1" \
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: "=q" (__result), "=m" (*mem) \
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: "0" (__addval), "m" (*mem), \
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"i" (offsetof (tcbhead_t, multiple_threads))); \
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else if (sizeof (*mem) == 2) \
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__asm __volatile (lock "xaddw %w0, %1" \
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: "=r" (__result), "=m" (*mem) \
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: "0" (__addval), "m" (*mem), \
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"i" (offsetof (tcbhead_t, multiple_threads))); \
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else if (sizeof (*mem) == 4) \
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__asm __volatile (lock "xaddl %0, %1" \
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: "=r" (__result), "=m" (*mem) \
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: "0" (__addval), "m" (*mem), \
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"i" (offsetof (tcbhead_t, multiple_threads))); \
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else \
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{ \
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__typeof (mem) __memp = (mem); \
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__typeof (*mem) __tmpval; \
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__result = *__memp; \
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do \
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__tmpval = __result; \
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while ((__result = pfx##_compare_and_exchange_val_64_acq \
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(__memp, __result + __addval, __result)) == __tmpval); \
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} \
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__result; })
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#define atomic_exchange_and_add(mem, value) \
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__sync_fetch_and_add (mem, value)
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#define __arch_exchange_and_add_cprefix \
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"cmpl $0, %%gs:%P4\n\tje 0f\n\tlock\n0:\t"
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#define catomic_exchange_and_add(mem, value) \
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__arch_exchange_and_add_body (__arch_exchange_and_add_cprefix, __arch_c, \
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mem, value)
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#define __arch_add_body(lock, pfx, mem, value) \
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do { \
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if (__builtin_constant_p (value) && (value) == 1) \
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atomic_increment (mem); \
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else if (__builtin_constant_p (value) && (value) == -1) \
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atomic_decrement (mem); \
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else if (sizeof (*mem) == 1) \
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__asm __volatile (lock "addb %b1, %0" \
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: "=m" (*mem) \
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: "iq" (value), "m" (*mem), \
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"i" (offsetof (tcbhead_t, multiple_threads))); \
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else if (sizeof (*mem) == 2) \
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__asm __volatile (lock "addw %w1, %0" \
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: "=m" (*mem) \
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: "ir" (value), "m" (*mem), \
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"i" (offsetof (tcbhead_t, multiple_threads))); \
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else if (sizeof (*mem) == 4) \
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__asm __volatile (lock "addl %1, %0" \
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: "=m" (*mem) \
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: "ir" (value), "m" (*mem), \
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"i" (offsetof (tcbhead_t, multiple_threads))); \
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else \
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{ \
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__typeof (value) __addval = (value); \
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__typeof (mem) __memp = (mem); \
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__typeof (*mem) __oldval = *__memp; \
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__typeof (*mem) __tmpval; \
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do \
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__tmpval = __oldval; \
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while ((__oldval = pfx##_compare_and_exchange_val_64_acq \
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(__memp, __oldval + __addval, __oldval)) == __tmpval); \
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} \
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} while (0)
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#define atomic_add(mem, value) \
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__arch_add_body (LOCK_PREFIX, __arch, mem, value)
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#define __arch_add_cprefix \
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"cmpl $0, %%gs:%P3\n\tje 0f\n\tlock\n0:\t"
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#define catomic_add(mem, value) \
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__arch_add_body (__arch_add_cprefix, __arch_c, mem, value)
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#define atomic_add_negative(mem, value) \
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({ unsigned char __result; \
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if (sizeof (*mem) == 1) \
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__asm __volatile (LOCK_PREFIX "addb %b2, %0; sets %1" \
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: "=m" (*mem), "=qm" (__result) \
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: "iq" (value), "m" (*mem)); \
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else if (sizeof (*mem) == 2) \
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__asm __volatile (LOCK_PREFIX "addw %w2, %0; sets %1" \
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: "=m" (*mem), "=qm" (__result) \
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: "ir" (value), "m" (*mem)); \
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else if (sizeof (*mem) == 4) \
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__asm __volatile (LOCK_PREFIX "addl %2, %0; sets %1" \
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: "=m" (*mem), "=qm" (__result) \
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: "ir" (value), "m" (*mem)); \
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else \
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abort (); \
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__result; })
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#define atomic_add_zero(mem, value) \
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({ unsigned char __result; \
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if (sizeof (*mem) == 1) \
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__asm __volatile (LOCK_PREFIX "addb %b2, %0; setz %1" \
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: "=m" (*mem), "=qm" (__result) \
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: "iq" (value), "m" (*mem)); \
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else if (sizeof (*mem) == 2) \
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__asm __volatile (LOCK_PREFIX "addw %w2, %0; setz %1" \
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: "=m" (*mem), "=qm" (__result) \
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: "ir" (value), "m" (*mem)); \
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else if (sizeof (*mem) == 4) \
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__asm __volatile (LOCK_PREFIX "addl %2, %0; setz %1" \
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: "=m" (*mem), "=qm" (__result) \
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: "ir" (value), "m" (*mem)); \
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else \
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abort (); \
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__result; })
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#define __arch_increment_body(lock, pfx, mem) \
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do { \
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if (sizeof (*mem) == 1) \
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__asm __volatile (lock "incb %b0" \
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: "=m" (*mem) \
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: "m" (*mem), \
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"i" (offsetof (tcbhead_t, multiple_threads))); \
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else if (sizeof (*mem) == 2) \
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__asm __volatile (lock "incw %w0" \
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: "=m" (*mem) \
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: "m" (*mem), \
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"i" (offsetof (tcbhead_t, multiple_threads))); \
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else if (sizeof (*mem) == 4) \
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__asm __volatile (lock "incl %0" \
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: "=m" (*mem) \
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: "m" (*mem), \
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"i" (offsetof (tcbhead_t, multiple_threads))); \
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else \
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{ \
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__typeof (mem) __memp = (mem); \
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__typeof (*mem) __oldval = *__memp; \
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__typeof (*mem) __tmpval; \
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do \
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__tmpval = __oldval; \
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while ((__oldval = pfx##_compare_and_exchange_val_64_acq \
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(__memp, __oldval + 1, __oldval)) == __tmpval); \
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} \
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} while (0)
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#define atomic_increment(mem) __arch_increment_body (LOCK_PREFIX, __arch, mem)
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#define __arch_increment_cprefix \
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"cmpl $0, %%gs:%P2\n\tje 0f\n\tlock\n0:\t"
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#define catomic_increment(mem) \
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__arch_increment_body (__arch_increment_cprefix, __arch_c, mem)
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#define atomic_increment_and_test(mem) \
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({ unsigned char __result; \
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if (sizeof (*mem) == 1) \
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__asm __volatile (LOCK_PREFIX "incb %0; sete %b1" \
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: "=m" (*mem), "=qm" (__result) \
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: "m" (*mem)); \
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else if (sizeof (*mem) == 2) \
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__asm __volatile (LOCK_PREFIX "incw %0; sete %w1" \
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: "=m" (*mem), "=qm" (__result) \
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: "m" (*mem)); \
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else if (sizeof (*mem) == 4) \
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__asm __volatile (LOCK_PREFIX "incl %0; sete %1" \
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: "=m" (*mem), "=qm" (__result) \
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: "m" (*mem)); \
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else \
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abort (); \
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__result; })
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#define __arch_decrement_body(lock, pfx, mem) \
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do { \
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if (sizeof (*mem) == 1) \
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__asm __volatile (lock "decb %b0" \
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: "=m" (*mem) \
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: "m" (*mem), \
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"i" (offsetof (tcbhead_t, multiple_threads))); \
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else if (sizeof (*mem) == 2) \
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__asm __volatile (lock "decw %w0" \
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: "=m" (*mem) \
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: "m" (*mem), \
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"i" (offsetof (tcbhead_t, multiple_threads))); \
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else if (sizeof (*mem) == 4) \
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__asm __volatile (lock "decl %0" \
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: "=m" (*mem) \
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: "m" (*mem), \
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"i" (offsetof (tcbhead_t, multiple_threads))); \
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else \
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{ \
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__typeof (mem) __memp = (mem); \
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__typeof (*mem) __oldval = *__memp; \
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__typeof (*mem) __tmpval; \
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do \
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__tmpval = __oldval; \
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while ((__oldval = pfx##_compare_and_exchange_val_64_acq \
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(__memp, __oldval - 1, __oldval)) == __tmpval); \
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} \
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} while (0)
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#define atomic_decrement(mem) __arch_decrement_body (LOCK_PREFIX, __arch, mem)
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#define __arch_decrement_cprefix \
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"cmpl $0, %%gs:%P2\n\tje 0f\n\tlock\n0:\t"
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#define catomic_decrement(mem) \
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__arch_decrement_body (__arch_decrement_cprefix, __arch_c, mem)
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#define atomic_decrement_and_test(mem) \
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({ unsigned char __result; \
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if (sizeof (*mem) == 1) \
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__asm __volatile (LOCK_PREFIX "decb %b0; sete %1" \
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: "=m" (*mem), "=qm" (__result) \
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: "m" (*mem)); \
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else if (sizeof (*mem) == 2) \
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__asm __volatile (LOCK_PREFIX "decw %w0; sete %1" \
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: "=m" (*mem), "=qm" (__result) \
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: "m" (*mem)); \
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else if (sizeof (*mem) == 4) \
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__asm __volatile (LOCK_PREFIX "decl %0; sete %1" \
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: "=m" (*mem), "=qm" (__result) \
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: "m" (*mem)); \
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else \
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abort (); \
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__result; })
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#define atomic_bit_set(mem, bit) \
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do { \
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if (sizeof (*mem) == 1) \
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__asm __volatile (LOCK_PREFIX "orb %b2, %0" \
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: "=m" (*mem) \
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: "m" (*mem), "iq" (1 << (bit))); \
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else if (sizeof (*mem) == 2) \
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__asm __volatile (LOCK_PREFIX "orw %w2, %0" \
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: "=m" (*mem) \
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: "m" (*mem), "ir" (1 << (bit))); \
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else if (sizeof (*mem) == 4) \
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__asm __volatile (LOCK_PREFIX "orl %2, %0" \
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: "=m" (*mem) \
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: "m" (*mem), "ir" (1 << (bit))); \
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else \
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abort (); \
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} while (0)
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#define atomic_bit_test_set(mem, bit) \
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({ unsigned char __result; \
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if (sizeof (*mem) == 1) \
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__asm __volatile (LOCK_PREFIX "btsb %3, %1; setc %0" \
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: "=q" (__result), "=m" (*mem) \
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: "m" (*mem), "ir" (bit)); \
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else if (sizeof (*mem) == 2) \
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__asm __volatile (LOCK_PREFIX "btsw %3, %1; setc %0" \
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: "=q" (__result), "=m" (*mem) \
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: "m" (*mem), "ir" (bit)); \
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else if (sizeof (*mem) == 4) \
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__asm __volatile (LOCK_PREFIX "btsl %3, %1; setc %0" \
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: "=q" (__result), "=m" (*mem) \
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: "m" (*mem), "ir" (bit)); \
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else \
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abort (); \
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__result; })
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#define atomic_spin_nop() asm ("rep; nop")
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#define __arch_and_body(lock, mem, mask) \
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do { \
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if (sizeof (*mem) == 1) \
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__asm __volatile (lock "andb %b1, %0" \
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: "=m" (*mem) \
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: "iq" (mask), "m" (*mem), \
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"i" (offsetof (tcbhead_t, multiple_threads))); \
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else if (sizeof (*mem) == 2) \
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__asm __volatile (lock "andw %w1, %0" \
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: "=m" (*mem) \
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: "ir" (mask), "m" (*mem), \
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"i" (offsetof (tcbhead_t, multiple_threads))); \
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else if (sizeof (*mem) == 4) \
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__asm __volatile (lock "andl %1, %0" \
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: "=m" (*mem) \
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: "ir" (mask), "m" (*mem), \
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"i" (offsetof (tcbhead_t, multiple_threads))); \
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else \
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abort (); \
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} while (0)
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#define __arch_cprefix \
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"cmpl $0, %%gs:%P3\n\tje 0f\n\tlock\n0:\t"
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#define atomic_and(mem, mask) __arch_and_body (LOCK_PREFIX, mem, mask)
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#define catomic_and(mem, mask) __arch_and_body (__arch_cprefix, mem, mask)
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#define __arch_or_body(lock, mem, mask) \
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do { \
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if (sizeof (*mem) == 1) \
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__asm __volatile (lock "orb %b1, %0" \
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: "=m" (*mem) \
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: "iq" (mask), "m" (*mem), \
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"i" (offsetof (tcbhead_t, multiple_threads))); \
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else if (sizeof (*mem) == 2) \
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__asm __volatile (lock "orw %w1, %0" \
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: "=m" (*mem) \
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: "ir" (mask), "m" (*mem), \
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"i" (offsetof (tcbhead_t, multiple_threads))); \
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else if (sizeof (*mem) == 4) \
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__asm __volatile (lock "orl %1, %0" \
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: "=m" (*mem) \
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: "ir" (mask), "m" (*mem), \
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"i" (offsetof (tcbhead_t, multiple_threads))); \
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else \
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abort (); \
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} while (0)
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#define atomic_or(mem, mask) __arch_or_body (LOCK_PREFIX, mem, mask)
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#define catomic_or(mem, mask) __arch_or_body (__arch_cprefix, mem, mask)
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/* We don't use mfence because it is supposedly slower due to having to
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provide stronger guarantees (e.g., regarding self-modifying code). */
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#define atomic_full_barrier() \
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__asm __volatile (LOCK_PREFIX "orl $0, (%%esp)" ::: "memory")
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#define atomic_read_barrier() __asm ("" ::: "memory")
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#define atomic_write_barrier() __asm ("" ::: "memory")
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