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b6a02c3606
1. Refactor files so that all implementations are in the multiarch
directory
- Moved the implementation portion of memmove sse2 from memmove.S
to multiarch/memmove-sse2.S
- The non-multiarch file now only includes one of the
implementations in the multiarch directory based on the compiled
ISA level (only used for non-multiarch builds. Otherwise we go
through the ifunc selector).
2. Add ISA level build guards to different implementations.
- I.e memmove-avx2-unaligned-erms.S which is ISA level 3 will only
build if compiled ISA level <= 3. Otherwise there is no reason
to include it as we will always use one of the ISA level 4
implementations (memmove-evex-unaligned-erms.S).
3. Add new multiarch/rtld-memmove.S that just include the
non-multiarch memmove.S which will in turn select the best
implementation based on the compiled ISA level.
4. Refactor the ifunc selector and ifunc implementation list to use
the ISA level aware wrapper macros that allow functions below the
compiled ISA level (with a guranteed replacement) to be skipped.
Tested with and without multiarch on x86_64 for ISA levels:
{generic, x86-64-v2, x86-64-v3, x86-64-v4}
And m32 with and without multiarch.
isa raising memmove
415 lines
9.0 KiB
ArmAsm
415 lines
9.0 KiB
ArmAsm
/* memmove/memcpy/mempcpy optimized for aligned access with SSSE3.
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All versions must be listed in ifunc-impl-list.c.
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Copyright (C) 2022 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<https://www.gnu.org/licenses/>. */
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#include <isa-level.h>
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#if ISA_SHOULD_BUILD (2)
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# include <sysdep.h>
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# ifndef MEMMOVE
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# define MEMMOVE __memmove_ssse3
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# define MEMMOVE_CHK __memmove_chk_ssse3
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# define MEMCPY __memcpy_ssse3
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# define MEMCPY_CHK __memcpy_chk_ssse3
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# define MEMPCPY __mempcpy_ssse3
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# define MEMPCPY_CHK __mempcpy_chk_ssse3
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# endif
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.section .text.ssse3, "ax", @progbits
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# if defined SHARED
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ENTRY(MEMPCPY_CHK)
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cmp %RDX_LP, %RCX_LP
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jb HIDDEN_JUMPTARGET(__chk_fail)
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END(MEMPCPY_CHK)
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# endif
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ENTRY(MEMPCPY)
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mov %RDI_LP, %RAX_LP
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add %RDX_LP, %RAX_LP
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jmp L(start)
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END(MEMPCPY)
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# if defined SHARED
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ENTRY(MEMMOVE_CHK)
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cmp %RDX_LP, %RCX_LP
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jb HIDDEN_JUMPTARGET(__chk_fail)
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END(MEMMOVE_CHK)
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# endif
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ENTRY_P2ALIGN(MEMMOVE, 6)
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# ifdef __ILP32__
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/* Clear the upper 32 bits. */
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movl %edx, %edx
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# endif
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movq %rdi, %rax
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L(start):
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cmpq $16, %rdx
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jb L(copy_0_15)
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/* These loads are always useful. */
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movups 0(%rsi), %xmm0
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movups -16(%rsi, %rdx), %xmm7
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cmpq $32, %rdx
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ja L(more_2x_vec)
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movups %xmm0, 0(%rdi)
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movups %xmm7, -16(%rdi, %rdx)
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ret
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.p2align 4,, 4
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L(copy_0_15):
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cmpl $4, %edx
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jb L(copy_0_3)
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cmpl $8, %edx
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jb L(copy_4_7)
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movq 0(%rsi), %rcx
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movq -8(%rsi, %rdx), %rsi
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movq %rcx, 0(%rdi)
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movq %rsi, -8(%rdi, %rdx)
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ret
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.p2align 4,, 4
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L(copy_4_7):
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movl 0(%rsi), %ecx
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movl -4(%rsi, %rdx), %esi
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movl %ecx, 0(%rdi)
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movl %esi, -4(%rdi, %rdx)
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ret
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.p2align 4,, 4
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L(copy_0_3):
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decl %edx
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jl L(copy_0_0)
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movb (%rsi), %cl
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je L(copy_1_1)
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movzwl -1(%rsi, %rdx), %esi
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movw %si, -1(%rdi, %rdx)
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L(copy_1_1):
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movb %cl, (%rdi)
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L(copy_0_0):
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ret
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.p2align 4,, 4
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L(copy_4x_vec):
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movups 16(%rsi), %xmm1
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movups -32(%rsi, %rdx), %xmm2
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movups %xmm0, 0(%rdi)
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movups %xmm1, 16(%rdi)
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movups %xmm2, -32(%rdi, %rdx)
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movups %xmm7, -16(%rdi, %rdx)
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L(nop):
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ret
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.p2align 4
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L(more_2x_vec):
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cmpq $64, %rdx
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jbe L(copy_4x_vec)
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/* We use rcx later to get alignr value. */
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movq %rdi, %rcx
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/* Backward copy for overlap + dst > src for memmove safety. */
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subq %rsi, %rcx
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cmpq %rdx, %rcx
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jb L(copy_backward)
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/* Load tail. */
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/* -16(%rsi, %rdx) already loaded into xmm7. */
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movups -32(%rsi, %rdx), %xmm8
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movups -48(%rsi, %rdx), %xmm9
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/* Get misalignment. */
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andl $0xf, %ecx
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movq %rsi, %r9
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addq %rcx, %rsi
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andq $-16, %rsi
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/* Get first vec for `palignr`. */
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movaps (%rsi), %xmm1
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/* We have loaded (%rsi) so safe to do this store before the
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loop. */
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movups %xmm0, (%rdi)
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# ifdef SHARED_CACHE_SIZE_HALF
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cmp $SHARED_CACHE_SIZE_HALF, %RDX_LP
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# else
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cmp __x86_shared_cache_size_half(%rip), %rdx
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# endif
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ja L(large_memcpy)
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leaq -64(%rdi, %rdx), %r8
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andq $-16, %rdi
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movl $48, %edx
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leaq L(loop_fwd_start)(%rip), %r9
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sall $6, %ecx
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addq %r9, %rcx
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jmp * %rcx
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.p2align 4,, 8
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L(copy_backward):
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testq %rcx, %rcx
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jz L(nop)
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/* Preload tail. */
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/* (%rsi) already loaded into xmm0. */
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movups 16(%rsi), %xmm4
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movups 32(%rsi), %xmm5
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movq %rdi, %r8
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subq %rdi, %rsi
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leaq -49(%rdi, %rdx), %rdi
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andq $-16, %rdi
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addq %rdi, %rsi
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andq $-16, %rsi
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movaps 48(%rsi), %xmm6
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leaq L(loop_bkwd_start)(%rip), %r9
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andl $0xf, %ecx
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sall $6, %ecx
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addq %r9, %rcx
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jmp * %rcx
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.p2align 4,, 8
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L(large_memcpy):
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movups -64(%r9, %rdx), %xmm10
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movups -80(%r9, %rdx), %xmm11
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sall $5, %ecx
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leal (%rcx, %rcx, 2), %r8d
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leaq -96(%rdi, %rdx), %rcx
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andq $-16, %rdi
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leaq L(large_loop_fwd_start)(%rip), %rdx
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addq %r8, %rdx
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jmp * %rdx
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/* Instead of a typical jump table all 16 loops are exactly
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64-bytes in size. So, we can just jump to first loop + r8 *
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64. Before modifying any loop ensure all their sizes match!
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*/
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.p2align 6
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L(loop_fwd_start):
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L(loop_fwd_0x0):
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movaps 16(%rsi), %xmm1
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movaps 32(%rsi), %xmm2
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movaps 48(%rsi), %xmm3
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movaps %xmm1, 16(%rdi)
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movaps %xmm2, 32(%rdi)
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movaps %xmm3, 48(%rdi)
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addq %rdx, %rdi
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addq %rdx, %rsi
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cmpq %rdi, %r8
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ja L(loop_fwd_0x0)
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L(end_loop_fwd):
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movups %xmm9, 16(%r8)
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movups %xmm8, 32(%r8)
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movups %xmm7, 48(%r8)
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ret
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/* Extactly 64 bytes if `jmp L(end_loop_fwd)` is long encoding.
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60 bytes otherwise. */
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# define ALIGNED_LOOP_FWD(align_by); \
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.p2align 6; \
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L(loop_fwd_ ## align_by): \
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movaps 16(%rsi), %xmm0; \
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movaps 32(%rsi), %xmm2; \
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movaps 48(%rsi), %xmm3; \
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movaps %xmm3, %xmm4; \
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palignr $align_by, %xmm2, %xmm3; \
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palignr $align_by, %xmm0, %xmm2; \
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palignr $align_by, %xmm1, %xmm0; \
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movaps %xmm4, %xmm1; \
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movaps %xmm0, 16(%rdi); \
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movaps %xmm2, 32(%rdi); \
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movaps %xmm3, 48(%rdi); \
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addq %rdx, %rdi; \
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addq %rdx, %rsi; \
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cmpq %rdi, %r8; \
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ja L(loop_fwd_ ## align_by); \
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jmp L(end_loop_fwd);
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/* Must be in descending order. */
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ALIGNED_LOOP_FWD (0xf)
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ALIGNED_LOOP_FWD (0xe)
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ALIGNED_LOOP_FWD (0xd)
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ALIGNED_LOOP_FWD (0xc)
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ALIGNED_LOOP_FWD (0xb)
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ALIGNED_LOOP_FWD (0xa)
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ALIGNED_LOOP_FWD (0x9)
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ALIGNED_LOOP_FWD (0x8)
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ALIGNED_LOOP_FWD (0x7)
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ALIGNED_LOOP_FWD (0x6)
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ALIGNED_LOOP_FWD (0x5)
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ALIGNED_LOOP_FWD (0x4)
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ALIGNED_LOOP_FWD (0x3)
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ALIGNED_LOOP_FWD (0x2)
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ALIGNED_LOOP_FWD (0x1)
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.p2align 6
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L(large_loop_fwd_start):
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L(large_loop_fwd_0x0):
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movaps 16(%rsi), %xmm1
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movaps 32(%rsi), %xmm2
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movaps 48(%rsi), %xmm3
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movaps 64(%rsi), %xmm4
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movaps 80(%rsi), %xmm5
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movntps %xmm1, 16(%rdi)
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movntps %xmm2, 32(%rdi)
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movntps %xmm3, 48(%rdi)
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movntps %xmm4, 64(%rdi)
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movntps %xmm5, 80(%rdi)
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addq $80, %rdi
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addq $80, %rsi
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cmpq %rdi, %rcx
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ja L(large_loop_fwd_0x0)
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/* Ensure no icache line split on tail. */
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.p2align 4
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L(end_large_loop_fwd):
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sfence
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movups %xmm11, 16(%rcx)
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movups %xmm10, 32(%rcx)
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movups %xmm9, 48(%rcx)
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movups %xmm8, 64(%rcx)
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movups %xmm7, 80(%rcx)
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ret
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/* Size > 64 bytes and <= 96 bytes. 32-byte align between ensure
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96-byte spacing between each. */
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# define ALIGNED_LARGE_LOOP_FWD(align_by); \
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.p2align 5; \
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L(large_loop_fwd_ ## align_by): \
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movaps 16(%rsi), %xmm0; \
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movaps 32(%rsi), %xmm2; \
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movaps 48(%rsi), %xmm3; \
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movaps 64(%rsi), %xmm4; \
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movaps 80(%rsi), %xmm5; \
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movaps %xmm5, %xmm6; \
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palignr $align_by, %xmm4, %xmm5; \
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palignr $align_by, %xmm3, %xmm4; \
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palignr $align_by, %xmm2, %xmm3; \
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palignr $align_by, %xmm0, %xmm2; \
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palignr $align_by, %xmm1, %xmm0; \
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movaps %xmm6, %xmm1; \
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movntps %xmm0, 16(%rdi); \
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movntps %xmm2, 32(%rdi); \
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movntps %xmm3, 48(%rdi); \
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movntps %xmm4, 64(%rdi); \
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movntps %xmm5, 80(%rdi); \
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addq $80, %rdi; \
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addq $80, %rsi; \
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cmpq %rdi, %rcx; \
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ja L(large_loop_fwd_ ## align_by); \
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jmp L(end_large_loop_fwd);
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/* Must be in descending order. */
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ALIGNED_LARGE_LOOP_FWD (0xf)
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ALIGNED_LARGE_LOOP_FWD (0xe)
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ALIGNED_LARGE_LOOP_FWD (0xd)
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ALIGNED_LARGE_LOOP_FWD (0xc)
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ALIGNED_LARGE_LOOP_FWD (0xb)
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ALIGNED_LARGE_LOOP_FWD (0xa)
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ALIGNED_LARGE_LOOP_FWD (0x9)
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ALIGNED_LARGE_LOOP_FWD (0x8)
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ALIGNED_LARGE_LOOP_FWD (0x7)
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ALIGNED_LARGE_LOOP_FWD (0x6)
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ALIGNED_LARGE_LOOP_FWD (0x5)
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ALIGNED_LARGE_LOOP_FWD (0x4)
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ALIGNED_LARGE_LOOP_FWD (0x3)
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ALIGNED_LARGE_LOOP_FWD (0x2)
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ALIGNED_LARGE_LOOP_FWD (0x1)
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.p2align 6
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L(loop_bkwd_start):
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L(loop_bkwd_0x0):
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movaps 32(%rsi), %xmm1
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movaps 16(%rsi), %xmm2
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movaps 0(%rsi), %xmm3
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movaps %xmm1, 32(%rdi)
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movaps %xmm2, 16(%rdi)
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movaps %xmm3, 0(%rdi)
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subq $48, %rdi
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subq $48, %rsi
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cmpq %rdi, %r8
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jb L(loop_bkwd_0x0)
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L(end_loop_bkwd):
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movups %xmm7, -16(%r8, %rdx)
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movups %xmm0, 0(%r8)
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movups %xmm4, 16(%r8)
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movups %xmm5, 32(%r8)
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ret
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/* Extactly 64 bytes if `jmp L(end_loop_bkwd)` is long encoding.
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60 bytes otherwise. */
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# define ALIGNED_LOOP_BKWD(align_by); \
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.p2align 6; \
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L(loop_bkwd_ ## align_by): \
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movaps 32(%rsi), %xmm1; \
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movaps 16(%rsi), %xmm2; \
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movaps 0(%rsi), %xmm3; \
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palignr $align_by, %xmm1, %xmm6; \
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palignr $align_by, %xmm2, %xmm1; \
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palignr $align_by, %xmm3, %xmm2; \
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movaps %xmm6, 32(%rdi); \
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movaps %xmm1, 16(%rdi); \
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movaps %xmm2, 0(%rdi); \
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subq $48, %rdi; \
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subq $48, %rsi; \
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movaps %xmm3, %xmm6; \
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cmpq %rdi, %r8; \
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jb L(loop_bkwd_ ## align_by); \
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jmp L(end_loop_bkwd);
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/* Must be in descending order. */
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ALIGNED_LOOP_BKWD (0xf)
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ALIGNED_LOOP_BKWD (0xe)
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ALIGNED_LOOP_BKWD (0xd)
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ALIGNED_LOOP_BKWD (0xc)
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ALIGNED_LOOP_BKWD (0xb)
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ALIGNED_LOOP_BKWD (0xa)
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ALIGNED_LOOP_BKWD (0x9)
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ALIGNED_LOOP_BKWD (0x8)
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ALIGNED_LOOP_BKWD (0x7)
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ALIGNED_LOOP_BKWD (0x6)
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ALIGNED_LOOP_BKWD (0x5)
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ALIGNED_LOOP_BKWD (0x4)
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ALIGNED_LOOP_BKWD (0x3)
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ALIGNED_LOOP_BKWD (0x2)
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ALIGNED_LOOP_BKWD (0x1)
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END(MEMMOVE)
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strong_alias (MEMMOVE, MEMCPY)
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# if defined SHARED
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strong_alias (MEMMOVE_CHK, MEMCPY_CHK)
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# endif
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#endif
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