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16d12015c5
No bug. This commit optimizes memcmp-avx2.S. The optimizations include adding a new vec compare path for small sizes, reorganizing the entry control flow, and removing some unnecissary ALU instructions from the main loop. test-memcmp and test-wmemcmp are both passing. Signed-off-by: Noah Goldstein <goldstein.w.n@gmail.com> Reviewed-by: H.J. Lu <hjl.tools@gmail.com>
545 lines
13 KiB
ArmAsm
545 lines
13 KiB
ArmAsm
/* memcmp/wmemcmp optimized with AVX2.
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Copyright (C) 2017-2021 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<https://www.gnu.org/licenses/>. */
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#if IS_IN (libc)
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/* memcmp/wmemcmp is implemented as:
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1. Use ymm vector compares when possible. The only case where
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vector compares is not possible for when size < VEC_SIZE
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and loading from either s1 or s2 would cause a page cross.
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2. For size from 2 to 7 bytes on page cross, load as big endian
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with movbe and bswap to avoid branches.
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3. Use xmm vector compare when size >= 4 bytes for memcmp or
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size >= 8 bytes for wmemcmp.
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4. Optimistically compare up to first 4 * VEC_SIZE one at a
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to check for early mismatches. Only do this if its guranteed the
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work is not wasted.
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5. If size is 8 * VEC_SIZE or less, unroll the loop.
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6. Compare 4 * VEC_SIZE at a time with the aligned first memory
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area.
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7. Use 2 vector compares when size is 2 * VEC_SIZE or less.
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8. Use 4 vector compares when size is 4 * VEC_SIZE or less.
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9. Use 8 vector compares when size is 8 * VEC_SIZE or less. */
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# include <sysdep.h>
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# ifndef MEMCMP
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# define MEMCMP __memcmp_avx2_movbe
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# endif
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# ifdef USE_AS_WMEMCMP
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# define CHAR_SIZE 4
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# define VPCMPEQ vpcmpeqd
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# else
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# define CHAR_SIZE 1
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# define VPCMPEQ vpcmpeqb
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# endif
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# ifndef VZEROUPPER
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# define VZEROUPPER vzeroupper
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# endif
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# ifndef SECTION
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# define SECTION(p) p##.avx
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# endif
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# define VEC_SIZE 32
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# define PAGE_SIZE 4096
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/* Warning!
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wmemcmp has to use SIGNED comparison for elements.
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memcmp has to use UNSIGNED comparison for elemnts.
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*/
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.section SECTION(.text),"ax",@progbits
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ENTRY (MEMCMP)
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# ifdef USE_AS_WMEMCMP
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shl $2, %RDX_LP
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# elif defined __ILP32__
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/* Clear the upper 32 bits. */
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movl %edx, %edx
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# endif
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cmp $VEC_SIZE, %RDX_LP
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jb L(less_vec)
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/* From VEC to 2 * VEC. No branch when size == VEC_SIZE. */
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vmovdqu (%rsi), %ymm1
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VPCMPEQ (%rdi), %ymm1, %ymm1
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vpmovmskb %ymm1, %eax
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/* NB: eax must be destination register if going to
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L(return_vec_[0,2]). For L(return_vec_3 destination register
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must be ecx. */
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incl %eax
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jnz L(return_vec_0)
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cmpq $(VEC_SIZE * 2), %rdx
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jbe L(last_1x_vec)
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/* Check second VEC no matter what. */
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vmovdqu VEC_SIZE(%rsi), %ymm2
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VPCMPEQ VEC_SIZE(%rdi), %ymm2, %ymm2
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vpmovmskb %ymm2, %eax
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/* If all 4 VEC where equal eax will be all 1s so incl will
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overflow and set zero flag. */
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incl %eax
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jnz L(return_vec_1)
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/* Less than 4 * VEC. */
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cmpq $(VEC_SIZE * 4), %rdx
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jbe L(last_2x_vec)
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/* Check third and fourth VEC no matter what. */
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vmovdqu (VEC_SIZE * 2)(%rsi), %ymm3
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VPCMPEQ (VEC_SIZE * 2)(%rdi), %ymm3, %ymm3
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vpmovmskb %ymm3, %eax
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incl %eax
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jnz L(return_vec_2)
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vmovdqu (VEC_SIZE * 3)(%rsi), %ymm4
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VPCMPEQ (VEC_SIZE * 3)(%rdi), %ymm4, %ymm4
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vpmovmskb %ymm4, %ecx
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incl %ecx
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jnz L(return_vec_3)
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/* Go to 4x VEC loop. */
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cmpq $(VEC_SIZE * 8), %rdx
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ja L(more_8x_vec)
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/* Handle remainder of size = 4 * VEC + 1 to 8 * VEC without any
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branches. */
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/* Load first two VEC from s2 before adjusting addresses. */
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vmovdqu -(VEC_SIZE * 4)(%rsi, %rdx), %ymm1
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vmovdqu -(VEC_SIZE * 3)(%rsi, %rdx), %ymm2
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leaq -(4 * VEC_SIZE)(%rdi, %rdx), %rdi
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leaq -(4 * VEC_SIZE)(%rsi, %rdx), %rsi
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/* Wait to load from s1 until addressed adjust due to
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unlamination of microfusion with complex address mode. */
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VPCMPEQ (%rdi), %ymm1, %ymm1
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VPCMPEQ (VEC_SIZE)(%rdi), %ymm2, %ymm2
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vmovdqu (VEC_SIZE * 2)(%rsi), %ymm3
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VPCMPEQ (VEC_SIZE * 2)(%rdi), %ymm3, %ymm3
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vmovdqu (VEC_SIZE * 3)(%rsi), %ymm4
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VPCMPEQ (VEC_SIZE * 3)(%rdi), %ymm4, %ymm4
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/* Reduce VEC0 - VEC4. */
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vpand %ymm1, %ymm2, %ymm5
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vpand %ymm3, %ymm4, %ymm6
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vpand %ymm5, %ymm6, %ymm7
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vpmovmskb %ymm7, %ecx
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incl %ecx
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jnz L(return_vec_0_1_2_3)
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/* NB: eax must be zero to reach here. */
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VZEROUPPER_RETURN
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.p2align 4
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L(return_vec_0):
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tzcntl %eax, %eax
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# ifdef USE_AS_WMEMCMP
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movl (%rdi, %rax), %ecx
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xorl %edx, %edx
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cmpl (%rsi, %rax), %ecx
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/* NB: no partial register stall here because xorl zero idiom
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above. */
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setg %dl
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leal -1(%rdx, %rdx), %eax
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# else
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movzbl (%rsi, %rax), %ecx
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movzbl (%rdi, %rax), %eax
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subl %ecx, %eax
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# endif
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L(return_vzeroupper):
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ZERO_UPPER_VEC_REGISTERS_RETURN
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.p2align 4
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L(return_vec_1):
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tzcntl %eax, %eax
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# ifdef USE_AS_WMEMCMP
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movl VEC_SIZE(%rdi, %rax), %ecx
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xorl %edx, %edx
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cmpl VEC_SIZE(%rsi, %rax), %ecx
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setg %dl
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leal -1(%rdx, %rdx), %eax
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# else
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movzbl VEC_SIZE(%rsi, %rax), %ecx
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movzbl VEC_SIZE(%rdi, %rax), %eax
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subl %ecx, %eax
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# endif
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VZEROUPPER_RETURN
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.p2align 4
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L(return_vec_2):
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tzcntl %eax, %eax
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# ifdef USE_AS_WMEMCMP
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movl (VEC_SIZE * 2)(%rdi, %rax), %ecx
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xorl %edx, %edx
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cmpl (VEC_SIZE * 2)(%rsi, %rax), %ecx
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setg %dl
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leal -1(%rdx, %rdx), %eax
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# else
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movzbl (VEC_SIZE * 2)(%rsi, %rax), %ecx
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movzbl (VEC_SIZE * 2)(%rdi, %rax), %eax
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subl %ecx, %eax
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# endif
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VZEROUPPER_RETURN
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/* NB: p2align 5 here to ensure 4x loop is 32 byte aligned. */
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.p2align 5
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L(8x_return_vec_0_1_2_3):
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/* Returning from L(more_8x_vec) requires restoring rsi. */
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addq %rdi, %rsi
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L(return_vec_0_1_2_3):
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vpmovmskb %ymm1, %eax
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incl %eax
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jnz L(return_vec_0)
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vpmovmskb %ymm2, %eax
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incl %eax
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jnz L(return_vec_1)
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vpmovmskb %ymm3, %eax
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incl %eax
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jnz L(return_vec_2)
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L(return_vec_3):
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tzcntl %ecx, %ecx
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# ifdef USE_AS_WMEMCMP
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movl (VEC_SIZE * 3)(%rdi, %rcx), %eax
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xorl %edx, %edx
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cmpl (VEC_SIZE * 3)(%rsi, %rcx), %eax
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setg %dl
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leal -1(%rdx, %rdx), %eax
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# else
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movzbl (VEC_SIZE * 3)(%rdi, %rcx), %eax
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movzbl (VEC_SIZE * 3)(%rsi, %rcx), %ecx
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subl %ecx, %eax
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# endif
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VZEROUPPER_RETURN
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.p2align 4
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L(more_8x_vec):
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/* Set end of s1 in rdx. */
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leaq -(VEC_SIZE * 4)(%rdi, %rdx), %rdx
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/* rsi stores s2 - s1. This allows loop to only update one
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pointer. */
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subq %rdi, %rsi
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/* Align s1 pointer. */
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andq $-VEC_SIZE, %rdi
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/* Adjust because first 4x vec where check already. */
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subq $-(VEC_SIZE * 4), %rdi
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.p2align 4
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L(loop_4x_vec):
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/* rsi has s2 - s1 so get correct address by adding s1 (in rdi).
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*/
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vmovdqu (%rsi, %rdi), %ymm1
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VPCMPEQ (%rdi), %ymm1, %ymm1
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vmovdqu VEC_SIZE(%rsi, %rdi), %ymm2
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VPCMPEQ VEC_SIZE(%rdi), %ymm2, %ymm2
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vmovdqu (VEC_SIZE * 2)(%rsi, %rdi), %ymm3
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VPCMPEQ (VEC_SIZE * 2)(%rdi), %ymm3, %ymm3
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vmovdqu (VEC_SIZE * 3)(%rsi, %rdi), %ymm4
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VPCMPEQ (VEC_SIZE * 3)(%rdi), %ymm4, %ymm4
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vpand %ymm1, %ymm2, %ymm5
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vpand %ymm3, %ymm4, %ymm6
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vpand %ymm5, %ymm6, %ymm7
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vpmovmskb %ymm7, %ecx
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incl %ecx
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jnz L(8x_return_vec_0_1_2_3)
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subq $-(VEC_SIZE * 4), %rdi
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/* Check if s1 pointer at end. */
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cmpq %rdx, %rdi
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jb L(loop_4x_vec)
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subq %rdx, %rdi
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/* rdi has 4 * VEC_SIZE - remaining length. */
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cmpl $(VEC_SIZE * 3), %edi
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jae L(8x_last_1x_vec)
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/* Load regardless of branch. */
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vmovdqu (VEC_SIZE * 2)(%rsi, %rdx), %ymm3
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cmpl $(VEC_SIZE * 2), %edi
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jae L(8x_last_2x_vec)
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/* Check last 4 VEC. */
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vmovdqu (%rsi, %rdx), %ymm1
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VPCMPEQ (%rdx), %ymm1, %ymm1
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vmovdqu VEC_SIZE(%rsi, %rdx), %ymm2
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VPCMPEQ VEC_SIZE(%rdx), %ymm2, %ymm2
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VPCMPEQ (VEC_SIZE * 2)(%rdx), %ymm3, %ymm3
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vmovdqu (VEC_SIZE * 3)(%rsi, %rdx), %ymm4
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VPCMPEQ (VEC_SIZE * 3)(%rdx), %ymm4, %ymm4
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vpand %ymm1, %ymm2, %ymm5
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vpand %ymm3, %ymm4, %ymm6
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vpand %ymm5, %ymm6, %ymm7
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vpmovmskb %ymm7, %ecx
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/* Restore s1 pointer to rdi. */
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movq %rdx, %rdi
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incl %ecx
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jnz L(8x_return_vec_0_1_2_3)
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/* NB: eax must be zero to reach here. */
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VZEROUPPER_RETURN
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/* Only entry is from L(more_8x_vec). */
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.p2align 4
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L(8x_last_2x_vec):
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/* Check second to last VEC. rdx store end pointer of s1 and
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ymm3 has already been loaded with second to last VEC from s2.
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*/
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VPCMPEQ (VEC_SIZE * 2)(%rdx), %ymm3, %ymm3
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vpmovmskb %ymm3, %eax
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incl %eax
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jnz L(8x_return_vec_2)
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/* Check last VEC. */
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.p2align 4
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L(8x_last_1x_vec):
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vmovdqu (VEC_SIZE * 3)(%rsi, %rdx), %ymm4
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VPCMPEQ (VEC_SIZE * 3)(%rdx), %ymm4, %ymm4
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vpmovmskb %ymm4, %eax
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incl %eax
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jnz L(8x_return_vec_3)
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VZEROUPPER_RETURN
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.p2align 4
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L(last_2x_vec):
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/* Check second to last VEC. */
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vmovdqu -(VEC_SIZE * 2)(%rsi, %rdx), %ymm1
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VPCMPEQ -(VEC_SIZE * 2)(%rdi, %rdx), %ymm1, %ymm1
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vpmovmskb %ymm1, %eax
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incl %eax
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jnz L(return_vec_1_end)
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/* Check last VEC. */
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L(last_1x_vec):
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vmovdqu -(VEC_SIZE * 1)(%rsi, %rdx), %ymm1
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VPCMPEQ -(VEC_SIZE * 1)(%rdi, %rdx), %ymm1, %ymm1
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vpmovmskb %ymm1, %eax
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incl %eax
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jnz L(return_vec_0_end)
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VZEROUPPER_RETURN
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.p2align 4
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L(8x_return_vec_2):
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subq $VEC_SIZE, %rdx
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L(8x_return_vec_3):
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tzcntl %eax, %eax
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addq %rdx, %rax
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# ifdef USE_AS_WMEMCMP
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movl (VEC_SIZE * 3)(%rax), %ecx
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xorl %edx, %edx
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cmpl (VEC_SIZE * 3)(%rsi, %rax), %ecx
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setg %dl
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leal -1(%rdx, %rdx), %eax
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# else
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movzbl (VEC_SIZE * 3)(%rsi, %rax), %ecx
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movzbl (VEC_SIZE * 3)(%rax), %eax
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subl %ecx, %eax
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# endif
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VZEROUPPER_RETURN
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.p2align 4
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L(return_vec_1_end):
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tzcntl %eax, %eax
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addl %edx, %eax
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# ifdef USE_AS_WMEMCMP
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movl -(VEC_SIZE * 2)(%rdi, %rax), %ecx
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xorl %edx, %edx
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cmpl -(VEC_SIZE * 2)(%rsi, %rax), %ecx
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setg %dl
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leal -1(%rdx, %rdx), %eax
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# else
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movzbl -(VEC_SIZE * 2)(%rsi, %rax), %ecx
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movzbl -(VEC_SIZE * 2)(%rdi, %rax), %eax
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subl %ecx, %eax
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# endif
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VZEROUPPER_RETURN
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.p2align 4
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L(return_vec_0_end):
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tzcntl %eax, %eax
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addl %edx, %eax
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# ifdef USE_AS_WMEMCMP
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movl -VEC_SIZE(%rdi, %rax), %ecx
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xorl %edx, %edx
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cmpl -VEC_SIZE(%rsi, %rax), %ecx
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setg %dl
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leal -1(%rdx, %rdx), %eax
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# else
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movzbl -VEC_SIZE(%rsi, %rax), %ecx
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movzbl -VEC_SIZE(%rdi, %rax), %eax
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subl %ecx, %eax
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# endif
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VZEROUPPER_RETURN
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.p2align 4
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L(less_vec):
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/* Check if one or less CHAR. This is necessary for size = 0 but
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is also faster for size = CHAR_SIZE. */
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cmpl $CHAR_SIZE, %edx
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jbe L(one_or_less)
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/* Check if loading one VEC from either s1 or s2 could cause a
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page cross. This can have false positives but is by far the
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fastest method. */
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movl %edi, %eax
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orl %esi, %eax
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andl $(PAGE_SIZE - 1), %eax
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cmpl $(PAGE_SIZE - VEC_SIZE), %eax
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jg L(page_cross_less_vec)
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/* No page cross possible. */
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vmovdqu (%rsi), %ymm2
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VPCMPEQ (%rdi), %ymm2, %ymm2
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vpmovmskb %ymm2, %eax
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incl %eax
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/* Result will be zero if s1 and s2 match. Otherwise first set
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bit will be first mismatch. */
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bzhil %edx, %eax, %edx
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jnz L(return_vec_0)
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xorl %eax, %eax
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VZEROUPPER_RETURN
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.p2align 4
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L(page_cross_less_vec):
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/* if USE_AS_WMEMCMP it can only be 0, 4, 8, 12, 16, 20, 24, 28
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bytes. */
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cmpl $16, %edx
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jae L(between_16_31)
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# ifndef USE_AS_WMEMCMP
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cmpl $8, %edx
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jae L(between_8_15)
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cmpl $4, %edx
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jae L(between_4_7)
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/* Load as big endian to avoid branches. */
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movzwl (%rdi), %eax
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movzwl (%rsi), %ecx
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shll $8, %eax
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shll $8, %ecx
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bswap %eax
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bswap %ecx
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movzbl -1(%rdi, %rdx), %edi
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movzbl -1(%rsi, %rdx), %esi
|
|
orl %edi, %eax
|
|
orl %esi, %ecx
|
|
/* Subtraction is okay because the upper 8 bits are zero. */
|
|
subl %ecx, %eax
|
|
/* No ymm register was touched. */
|
|
ret
|
|
|
|
.p2align 4
|
|
L(one_or_less):
|
|
jb L(zero)
|
|
movzbl (%rsi), %ecx
|
|
movzbl (%rdi), %eax
|
|
subl %ecx, %eax
|
|
/* No ymm register was touched. */
|
|
ret
|
|
|
|
.p2align 4
|
|
L(between_8_15):
|
|
# endif
|
|
/* If USE_AS_WMEMCMP fall through into 8-15 byte case. */
|
|
vmovq (%rdi), %xmm1
|
|
vmovq (%rsi), %xmm2
|
|
VPCMPEQ %xmm1, %xmm2, %xmm2
|
|
vpmovmskb %xmm2, %eax
|
|
subl $0xffff, %eax
|
|
jnz L(return_vec_0)
|
|
/* Use overlapping loads to avoid branches. */
|
|
leaq -8(%rdi, %rdx), %rdi
|
|
leaq -8(%rsi, %rdx), %rsi
|
|
vmovq (%rdi), %xmm1
|
|
vmovq (%rsi), %xmm2
|
|
VPCMPEQ %xmm1, %xmm2, %xmm2
|
|
vpmovmskb %xmm2, %eax
|
|
subl $0xffff, %eax
|
|
jnz L(return_vec_0)
|
|
/* No ymm register was touched. */
|
|
ret
|
|
|
|
.p2align 4
|
|
L(zero):
|
|
xorl %eax, %eax
|
|
ret
|
|
|
|
.p2align 4
|
|
L(between_16_31):
|
|
/* From 16 to 31 bytes. No branch when size == 16. */
|
|
vmovdqu (%rsi), %xmm2
|
|
VPCMPEQ (%rdi), %xmm2, %xmm2
|
|
vpmovmskb %xmm2, %eax
|
|
subl $0xffff, %eax
|
|
jnz L(return_vec_0)
|
|
|
|
/* Use overlapping loads to avoid branches. */
|
|
|
|
vmovdqu -16(%rsi, %rdx), %xmm2
|
|
leaq -16(%rdi, %rdx), %rdi
|
|
leaq -16(%rsi, %rdx), %rsi
|
|
VPCMPEQ (%rdi), %xmm2, %xmm2
|
|
vpmovmskb %xmm2, %eax
|
|
subl $0xffff, %eax
|
|
jnz L(return_vec_0)
|
|
/* No ymm register was touched. */
|
|
ret
|
|
|
|
# ifdef USE_AS_WMEMCMP
|
|
.p2align 4
|
|
L(one_or_less):
|
|
jb L(zero)
|
|
movl (%rdi), %ecx
|
|
xorl %edx, %edx
|
|
cmpl (%rsi), %ecx
|
|
je L(zero)
|
|
setg %dl
|
|
leal -1(%rdx, %rdx), %eax
|
|
/* No ymm register was touched. */
|
|
ret
|
|
# else
|
|
|
|
.p2align 4
|
|
L(between_4_7):
|
|
/* Load as big endian with overlapping movbe to avoid branches.
|
|
*/
|
|
movbe (%rdi), %eax
|
|
movbe (%rsi), %ecx
|
|
shlq $32, %rax
|
|
shlq $32, %rcx
|
|
movbe -4(%rdi, %rdx), %edi
|
|
movbe -4(%rsi, %rdx), %esi
|
|
orq %rdi, %rax
|
|
orq %rsi, %rcx
|
|
subq %rcx, %rax
|
|
jz L(zero_4_7)
|
|
sbbl %eax, %eax
|
|
orl $1, %eax
|
|
L(zero_4_7):
|
|
/* No ymm register was touched. */
|
|
ret
|
|
# endif
|
|
|
|
END (MEMCMP)
|
|
#endif
|