glibc/sysdeps/unix/sysv/linux/aarch64/libmvec.abilist
Joe Ramsay 4a9392ffc2 aarch64: Add vector implementations of exp routines
Optimised implementations for single and double precision, Advanced
SIMD and SVE, copied from Arm Optimized Routines.

As previously, data tables are used via a barrier to prevent
overly aggressive constant inlining. Special-case handlers are
marked NOINLINE to avoid incurring the penalty of switching call
standards unnecessarily.

Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2023-06-30 09:04:26 +01:00

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GLIBC_2.38 _ZGVnN2v_cos F
GLIBC_2.38 _ZGVnN2v_exp F
GLIBC_2.38 _ZGVnN2v_log F
GLIBC_2.38 _ZGVnN2v_sin F
GLIBC_2.38 _ZGVnN4v_cosf F
GLIBC_2.38 _ZGVnN4v_expf F
GLIBC_2.38 _ZGVnN4v_logf F
GLIBC_2.38 _ZGVnN4v_sinf F
GLIBC_2.38 _ZGVsMxv_cos F
GLIBC_2.38 _ZGVsMxv_cosf F
GLIBC_2.38 _ZGVsMxv_exp F
GLIBC_2.38 _ZGVsMxv_expf F
GLIBC_2.38 _ZGVsMxv_log F
GLIBC_2.38 _ZGVsMxv_logf F
GLIBC_2.38 _ZGVsMxv_sin F
GLIBC_2.38 _ZGVsMxv_sinf F