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5bc100bd4b
log1pf is quite register-intensive - use fewer registers for the polynomial, and make various changes to shorten dependency chains in parent routines. There is now no spilling with GCC 14. Accuracy moves around a little - comments adjusted accordingly but does not require regen-ulps. Use the helper in log1pf as well, instead of having separate implementations. The more accurate polynomial means special-casing can be simplified, and the shorter dependency chain avoids the usual dance around v0, which is otherwise difficult. There is a small duplication of vectors containing 1.0f (or 0x3f800000) - GCC is not currently able to efficiently handle values which fit in FMOV but not MOVI, and are reinterpreted to integer. There may be potential for more optimisation if this is fixed. Reviewed-by: Wilco Dijkstra <Wilco.Dijkstra@arm.com>
90 lines
2.9 KiB
C
90 lines
2.9 KiB
C
/* Single-precision vector (Advanced SIMD) atanh function
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Copyright (C) 2024 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<https://www.gnu.org/licenses/>. */
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#include "v_math.h"
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#include "v_log1pf_inline.h"
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const static struct data
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{
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struct v_log1pf_data log1pf_consts;
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uint32x4_t one;
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#if WANT_SIMD_EXCEPT
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uint32x4_t tiny_bound;
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#endif
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} data = {
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.log1pf_consts = V_LOG1PF_CONSTANTS_TABLE,
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.one = V4 (0x3f800000),
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#if WANT_SIMD_EXCEPT
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/* 0x1p-12, below which atanhf(x) rounds to x. */
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.tiny_bound = V4 (0x39800000),
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#endif
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};
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#define AbsMask v_u32 (0x7fffffff)
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#define Half v_u32 (0x3f000000)
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static float32x4_t NOINLINE VPCS_ATTR
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special_case (float32x4_t x, float32x4_t halfsign, float32x4_t y,
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uint32x4_t special)
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{
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return v_call_f32 (atanhf, vbslq_f32 (AbsMask, x, halfsign),
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vmulq_f32 (halfsign, y), special);
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}
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/* Approximation for vector single-precision atanh(x) using modified log1p.
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The maximum error is 2.93 ULP:
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_ZGVnN4v_atanhf(0x1.f43d7p-5) got 0x1.f4dcfep-5
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want 0x1.f4dcf8p-5. */
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VPCS_ATTR float32x4_t NOINLINE V_NAME_F1 (atanh) (float32x4_t x)
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{
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const struct data *d = ptr_barrier (&data);
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float32x4_t halfsign = vbslq_f32 (AbsMask, v_f32 (0.5), x);
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float32x4_t ax = vabsq_f32 (x);
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uint32x4_t iax = vreinterpretq_u32_f32 (ax);
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#if WANT_SIMD_EXCEPT
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uint32x4_t special
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= vorrq_u32 (vcgeq_u32 (iax, d->one), vcltq_u32 (iax, d->tiny_bound));
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/* Side-step special cases by setting those lanes to 0, which will trigger no
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exceptions. These will be fixed up later. */
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if (__glibc_unlikely (v_any_u32 (special)))
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ax = v_zerofy_f32 (ax, special);
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#else
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uint32x4_t special = vcgeq_u32 (iax, d->one);
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#endif
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float32x4_t y = vdivq_f32 (vaddq_f32 (ax, ax),
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vsubq_f32 (vreinterpretq_f32_u32 (d->one), ax));
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y = log1pf_inline (y, &d->log1pf_consts);
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/* If exceptions not required, pass ax to special-case for shorter dependency
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chain. If exceptions are required ax will have been zerofied, so have to
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pass x. */
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if (__glibc_unlikely (v_any_u32 (special)))
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#if WANT_SIMD_EXCEPT
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return special_case (x, halfsign, y, special);
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#else
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return special_case (ax, halfsign, y, special);
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#endif
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return vmulq_f32 (halfsign, y);
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}
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libmvec_hidden_def (V_NAME_F1 (atanh))
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HALF_WIDTH_ALIAS_F1 (atanh)
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