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a15b1394b5
Reduce MOVPRFXs by using unpredicated (non-destructive) instructions where possible. Similar to the recent change to AdvSIMD F32 logs, adjust special-case arguments and bounds to allow for more optimal register usage. For all 3 routines one MOVPRFX remains in the reduction, which cannot be avoided as immediate AND and ASR are both destructive. Reviewed-by: Wilco Dijkstra <Wilco.Dijkstra@arm.com>
94 lines
3.4 KiB
C
94 lines
3.4 KiB
C
/* Single-precision vector (SVE) log function.
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Copyright (C) 2023-2024 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<https://www.gnu.org/licenses/>. */
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#include "sv_math.h"
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static const struct data
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{
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float poly_0135[4];
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float poly_246[3];
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float ln2;
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uint32_t off, lower;
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} data = {
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.poly_0135 = {
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/* Coefficients copied from the AdvSIMD routine in math/, then rearranged so
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that coeffs 0, 1, 3 and 5 can be loaded as a single quad-word, hence used
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with _lane variant of MLA intrinsic. */
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-0x1.3e737cp-3f, 0x1.5a9aa2p-3f, 0x1.961348p-3f, 0x1.555d7cp-2f
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},
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.poly_246 = { -0x1.4f9934p-3f, -0x1.00187cp-2f, -0x1.ffffc8p-2f },
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.ln2 = 0x1.62e43p-1f,
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.off = 0x3f2aaaab,
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/* Lower bound is the smallest positive normal float 0x00800000. For
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optimised register use subnormals are detected after offset has been
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subtracted, so lower bound is 0x0080000 - offset (which wraps around). */
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.lower = 0x00800000 - 0x3f2aaaab
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};
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#define Thresh (0x7f000000) /* asuint32(inf) - 0x00800000. */
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#define Mask (0x007fffff)
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static svfloat32_t NOINLINE
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special_case (svuint32_t u_off, svfloat32_t p, svfloat32_t r2, svfloat32_t y,
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svbool_t cmp)
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{
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return sv_call_f32 (
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logf, svreinterpret_f32 (svadd_x (svptrue_b32 (), u_off, data.off)),
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svmla_x (svptrue_b32 (), p, r2, y), cmp);
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}
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/* Optimised implementation of SVE logf, using the same algorithm and
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polynomial as the AdvSIMD routine. Maximum error is 3.34 ULPs:
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SV_NAME_F1 (log)(0x1.557298p+0) got 0x1.26edecp-2
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want 0x1.26ede6p-2. */
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svfloat32_t SV_NAME_F1 (log) (svfloat32_t x, const svbool_t pg)
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{
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const struct data *d = ptr_barrier (&data);
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svuint32_t u_off = svreinterpret_u32 (x);
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u_off = svsub_x (pg, u_off, d->off);
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svbool_t cmp = svcmpge (pg, svsub_x (pg, u_off, d->lower), Thresh);
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/* x = 2^n * (1+r), where 2/3 < 1+r < 4/3. */
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svfloat32_t n = svcvt_f32_x (
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pg, svasr_x (pg, svreinterpret_s32 (u_off), 23)); /* Sign-extend. */
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svuint32_t u = svand_x (pg, u_off, Mask);
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u = svadd_x (pg, u, d->off);
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svfloat32_t r = svsub_x (pg, svreinterpret_f32 (u), 1.0f);
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/* y = log(1+r) + n*ln2. */
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svfloat32_t r2 = svmul_x (svptrue_b32 (), r, r);
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/* n*ln2 + r + r2*(P6 + r*P5 + r2*(P4 + r*P3 + r2*(P2 + r*P1 + r2*P0))). */
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svfloat32_t p_0135 = svld1rq (svptrue_b32 (), &d->poly_0135[0]);
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svfloat32_t p = svmla_lane (sv_f32 (d->poly_246[0]), r, p_0135, 1);
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svfloat32_t q = svmla_lane (sv_f32 (d->poly_246[1]), r, p_0135, 2);
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svfloat32_t y = svmla_lane (sv_f32 (d->poly_246[2]), r, p_0135, 3);
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p = svmla_lane (p, r2, p_0135, 0);
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q = svmla_x (pg, q, r2, p);
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y = svmla_x (pg, y, r2, q);
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p = svmla_x (pg, r, n, d->ln2);
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if (__glibc_unlikely (svptest_any (pg, cmp)))
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return special_case (u_off, p, r2, y, cmp);
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return svmla_x (pg, p, r2, y);
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}
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