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46 lines
1.4 KiB
C
46 lines
1.4 KiB
C
/* Install given floating-point control modes. ARM version.
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Copyright (C) 2016-2023 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<https://www.gnu.org/licenses/>. */
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#include <fenv.h>
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#include <fpu_control.h>
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#include <arm-features.h>
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/* NZCV flags, QC bit, IDC bit and bits for IEEE exception status. */
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#define FPU_STATUS_BITS 0xf800009f
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int
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fesetmode (const femode_t *modep)
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{
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fpu_control_t fpscr, new_fpscr;
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if (!ARM_HAVE_VFP)
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/* Nothing to do. */
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return 0;
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_FPU_GETCW (fpscr);
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if (modep == FE_DFL_MODE)
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new_fpscr = (fpscr & (_FPU_RESERVED | FPU_STATUS_BITS)) | _FPU_DEFAULT;
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else
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new_fpscr = (fpscr & FPU_STATUS_BITS) | (*modep & ~FPU_STATUS_BITS);
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if (((new_fpscr ^ fpscr) & ~_FPU_MASK_NZCV) != 0)
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_FPU_SETCW (new_fpscr);
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return 0;
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}
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