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2008-11-13 Ryan S. Arnold <rsa@us.ibm.com> [BZ #6411] * sysdeps/powerpc/fpu/Makefile: Added test case tst-setcontext-fpscr. * sysdeps/powerpc/fpu/feholdexcpt.c (_FPU_MASK_ALL): Define to replace magic numbers. * sysdeps/powerpc/fpu/fenv_libc.h (fesetenv_register): Dynamically choose mtfsf insn based on PPC_FEATURE_HAS_DFP. (relax_fenv_state): Same as above. (FPSCR_29): Reserve bit in ISA 2.05. (FPSCR_NI): Provide define for compat. * sysdeps/powerpc/fpu/fesetenv.c (_FPU_MASK_ALL): Define to replace magic numbers. * sysdeps/powerpc/fpu/feupdateenv.c (_FPU_MASK_ALL): Define to replace magic numbers. * sysdeps/powerpc/fpu/tst-setcontext-fpscr.c: New file. Test case to test setcontext and swapcontext with dynamic 64-bit FPSCR detection. * sysdeps/powerpc/powerpc32/fpu/__longjmp-common.S (__longjmp): Adjust access to hwcap to account for hwcap size increase to uint64_t. * sysdeps/powerpc/powerpc32/fpu/setjmp-common.S (__sigsetjmp ): Likewise. * sysdeps/unix/sysv/linux/powerpc/powerpc32/getcontext-common.S (*setcontext): Likewise. * sysdeps/unix/sysv/linux/powerpc/powerpc32/power6/fpu/setcontext.S: New file. * sysdeps/unix/sysv/linux/powerpc/powerpc32/power6/fpu/swapcontext.S: New file. * sysdeps/unix/sysv/linux/powerpc/powerpc32/setcontext-common.S (*setcontext): dynamically select mtfsf insn based on PPC_FEATURE_HAS_DFP. Adjust access to hwcap to account for hwcap size increase to uint64_t. * sysdeps/unix/sysv/linux/powerpc/powerpc32/swapcontext-common.S (*swapcontext): dynamically select mtfsf insn based on PPC_FEATURE_HAS_DFP. Adjust access to hwcap to account for hwcap size increase to uint64_t. * sysdeps/unix/sysv/linux/powerpc/powerpc64/power6/fpu/setcontext.S: New file. * sysdeps/unix/sysv/linux/powerpc/powerpc64/power6/fpu/swapcontext.S: New file. * sysdeps/unix/sysv/linux/powerpc/powerpc64/setcontext.S (*setcontext): dynamically select mtfsf insn based on PPC_FEATURE_HAS_DFP. * sysdeps/unix/sysv/linux/powerpc/powerpc64/swapcontext.S (*swapcontext): dynamically select mtfsf insn based on PPC_FEATURE_HAS_DFP.
70 lines
2.7 KiB
C
70 lines
2.7 KiB
C
/* Install given floating-point environment and raise exceptions.
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Copyright (C) 1997, 1999, 2000, 2001, 2007, 2008
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Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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Contributed by Ulrich Drepper <drepper@cygnus.com>, 1997.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, write to the Free
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Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
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02111-1307 USA. */
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#include <fenv_libc.h>
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#include <fpu_control.h>
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#include <bp-sym.h>
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#define _FPU_MASK_ALL (_FPU_MASK_ZM | _FPU_MASK_OM | _FPU_MASK_UM | _FPU_MASK_XM | _FPU_MASK_IM)
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int
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__feupdateenv (const fenv_t *envp)
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{
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fenv_union_t old, new;
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/* Save the currently set exceptions. */
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new.fenv = *envp;
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old.fenv = fegetenv_register ();
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/* Restore rounding mode and exception enable from *envp and merge
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exceptions. Leave fraction rounded/inexact and FP result/CC bits
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unchanged. */
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new.l[1] = (old.l[1] & 0x1FFFFF00) | (new.l[1] & 0x1FF80FFF);
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/* If the old env has no eabled exceptions and the new env has any enabled
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exceptions, then unmask SIGFPE in the MSR FE0/FE1 bits. This will put
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the hardware into "precise mode" and may cause the FPU to run slower on
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some hardware. */
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if ((old.l[1] & _FPU_MASK_ALL) == 0 && (new.l[1] & _FPU_MASK_ALL) != 0)
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(void)__fe_nomask_env ();
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/* If the old env had any eabled exceptions and the new env has no enabled
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exceptions, then mask SIGFPE in the MSR FE0/FE1 bits. This may allow the
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FPU to run faster because it always takes the default action and can not
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generate SIGFPE. */
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if ((old.l[1] & _FPU_MASK_ALL) != 0 && (new.l[1] & _FPU_MASK_ALL) == 0)
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(void)__fe_mask_env ();
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/* Atomically enable and raise (if appropriate) exceptions set in `new'. */
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fesetenv_register (new.fenv);
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/* Success. */
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return 0;
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}
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#include <shlib-compat.h>
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#if SHLIB_COMPAT (libm, GLIBC_2_1, GLIBC_2_2)
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strong_alias (__feupdateenv, __old_feupdateenv)
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compat_symbol (libm, BP_SYM (__old_feupdateenv), BP_SYM (feupdateenv), GLIBC_2_1);
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#endif
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versioned_symbol (libm, BP_SYM (__feupdateenv), BP_SYM (feupdateenv), GLIBC_2_2);
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