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It's not legal for raw stores to be mixed with atomic operations on tilepro, since the atomics are managed by kernel fast syscalls. It's possible for a hardware store and a kernel fast atomic to race with each other in such a way that the hardware store is lost. Suppose you have an initial zero value, and you race with a store of 2 and a kernel cmpxchg from 0 to 1. The legal output is only 2: either the store hit first and the cmpxchg failed, or the cmpxchg hit first and succeeded, then was overwritten by the 2. But if the kernel cmpxchg starts first and loads the zero, then the store hits and sets the value to 2, the cmpxchg will still decide it was successful and write the 1, leaving the value illegally set to 1. Using atomic_exchange variants to implement atomic_store fixes this problem for tilepro.
99 lines
4.0 KiB
C
99 lines
4.0 KiB
C
/* Copyright (C) 2011-2016 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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Contributed by Chris Metcalf <cmetcalf@tilera.com>, 2011.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library. If not, see
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<http://www.gnu.org/licenses/>. */
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#ifndef _ATOMIC_MACHINE_H
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#define _ATOMIC_MACHINE_H 1
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#include <asm/unistd.h>
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#define __HAVE_64B_ATOMICS 0
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#define USE_ATOMIC_COMPILER_BUILTINS 0
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/* 32-bit integer compare-and-exchange. */
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static __inline __attribute__ ((always_inline))
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int __atomic_cmpxchg_32 (volatile int *mem, int newval, int oldval)
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{
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int result;
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__asm__ __volatile__ ("swint1"
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: "=R00" (result), "=m" (*mem)
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: "R10" (__NR_FAST_cmpxchg), "R00" (mem),
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"R01" (oldval), "R02" (newval), "m" (*mem)
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: "r20", "r21", "r22", "r23", "r24",
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"r25", "r26", "r27", "r28", "r29", "memory");
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return result;
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}
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#define atomic_compare_and_exchange_val_acq(mem, n, o) \
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({ \
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if (sizeof (*(mem)) != 4) \
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__atomic_error_bad_argument_size (); \
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(__typeof (*(mem))) \
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__atomic_cmpxchg_32 ((int *) (mem), (int) (n), (int) (o)); \
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})
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/* Atomically compute:
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int old = *ptr;
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*ptr = (old & mask) + addend;
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return old; */
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static __inline __attribute__ ((always_inline))
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int __atomic_update_32 (volatile int *mem, int mask, int addend)
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{
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int result;
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__asm__ __volatile__ ("swint1"
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: "=R00" (result), "=m" (*mem)
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: "R10" (__NR_FAST_atomic_update), "R00" (mem),
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"R01" (mask), "R02" (addend), "m" (*mem)
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: "r20", "r21", "r22", "r23", "r24",
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"r25", "r26", "r27", "r28", "r29", "memory");
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return result;
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}
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/* Size-checked verson of __atomic_update_32. */
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#define __atomic_update(mem, mask, addend) \
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({ \
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if (sizeof (*(mem)) != 4) \
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__atomic_error_bad_argument_size (); \
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(__typeof (*(mem))) \
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__atomic_update_32 ((int *) (mem), (int) (mask), (int) (addend)); \
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})
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#define atomic_exchange_acq(mem, newvalue) \
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__atomic_update ((mem), 0, (newvalue))
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#define atomic_exchange_and_add(mem, value) \
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__atomic_update ((mem), -1, (value))
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#define atomic_and_val(mem, mask) \
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__atomic_update ((mem), (mask), 0)
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#define atomic_or_val(mem, mask) \
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({ __typeof (mask) __att1_v = (mask); \
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__atomic_update ((mem), ~__att1_v, __att1_v); })
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/*
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* We must use the kernel atomics for atomic_store, since otherwise an
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* unsynchronized store could become visible after another core's
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* kernel-atomic implementation had read the memory word in question,
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* but before it had written the updated value to it, which would
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* cause the unsynchronized store to be lost.
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*/
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#define atomic_store_relaxed(mem, val) atomic_exchange_acq (mem, val)
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#define atomic_store_release(mem, val) atomic_exchange_rel (mem, val)
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#include <sysdeps/tile/atomic-machine.h>
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#endif /* atomic-machine.h */
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