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ceabdcd130
1. Add default ISA level selection in non-multiarch/rtld
implementations.
2. Add ISA level build guards to different implementations.
- I.e strcmp-avx2.S which is ISA level 3 will only build if
compiled ISA level <= 3. Otherwise there is no reason to
include it as we will always use one of the ISA level 4
implementations (strcmp-evex.S).
3. Refactor the ifunc selector and ifunc implementation list to use
the ISA level aware wrapper macros that allow functions below the
compiled ISA level (with a guranteed replacement) to be skipped.
Tested with and without multiarch on x86_64 for ISA levels:
{generic, x86-64-v2, x86-64-v3, x86-64-v4}
And m32 with and without multiarch.
341 lines
7.5 KiB
ArmAsm
341 lines
7.5 KiB
ArmAsm
/* memrchr optimized with AVX2.
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Copyright (C) 2017-2022 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<https://www.gnu.org/licenses/>. */
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#include <isa-level.h>
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#if ISA_SHOULD_BUILD (3)
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# include <sysdep.h>
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# ifndef MEMRCHR
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# define MEMRCHR __memrchr_avx2
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# endif
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# ifndef VZEROUPPER
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# define VZEROUPPER vzeroupper
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# endif
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# ifndef SECTION
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# define SECTION(p) p##.avx
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# endif
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# define VEC_SIZE 32
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# define PAGE_SIZE 4096
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.section SECTION(.text), "ax", @progbits
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ENTRY_P2ALIGN(MEMRCHR, 6)
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# ifdef __ILP32__
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/* Clear upper bits. */
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and %RDX_LP, %RDX_LP
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# else
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test %RDX_LP, %RDX_LP
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# endif
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jz L(zero_0)
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vmovd %esi, %xmm0
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/* Get end pointer. Minus one for two reasons. 1) It is necessary for a
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correct page cross check and 2) it correctly sets up end ptr to be
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subtract by lzcnt aligned. */
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leaq -1(%rdx, %rdi), %rax
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vpbroadcastb %xmm0, %ymm0
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/* Check if we can load 1x VEC without cross a page. */
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testl $(PAGE_SIZE - VEC_SIZE), %eax
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jz L(page_cross)
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vpcmpeqb -(VEC_SIZE - 1)(%rax), %ymm0, %ymm1
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vpmovmskb %ymm1, %ecx
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cmpq $VEC_SIZE, %rdx
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ja L(more_1x_vec)
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L(ret_vec_x0_test):
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/* If ecx is zero (no matches) lzcnt will set it 32 (VEC_SIZE) which
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will gurantee edx (len) is less than it. */
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lzcntl %ecx, %ecx
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/* Hoist vzeroupper (not great for RTM) to save code size. This allows
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all logic for edx (len) <= VEC_SIZE to fit in first cache line. */
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COND_VZEROUPPER
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cmpl %ecx, %edx
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jle L(zero_0)
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subq %rcx, %rax
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ret
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/* Fits in aligning bytes of first cache line. */
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L(zero_0):
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xorl %eax, %eax
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ret
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.p2align 4,, 9
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L(ret_vec_x0):
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lzcntl %ecx, %ecx
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subq %rcx, %rax
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L(return_vzeroupper):
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ZERO_UPPER_VEC_REGISTERS_RETURN
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.p2align 4,, 10
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L(more_1x_vec):
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testl %ecx, %ecx
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jnz L(ret_vec_x0)
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/* Align rax (string pointer). */
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andq $-VEC_SIZE, %rax
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/* Recompute remaining length after aligning. */
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movq %rax, %rdx
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/* Need this comparison next no matter what. */
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vpcmpeqb -(VEC_SIZE)(%rax), %ymm0, %ymm1
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subq %rdi, %rdx
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decq %rax
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vpmovmskb %ymm1, %ecx
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/* Fall through for short (hotter than length). */
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cmpq $(VEC_SIZE * 2), %rdx
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ja L(more_2x_vec)
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L(last_2x_vec):
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cmpl $VEC_SIZE, %edx
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jbe L(ret_vec_x0_test)
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testl %ecx, %ecx
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jnz L(ret_vec_x0)
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vpcmpeqb -(VEC_SIZE * 2 - 1)(%rax), %ymm0, %ymm1
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vpmovmskb %ymm1, %ecx
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/* 64-bit lzcnt. This will naturally add 32 to position. */
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lzcntq %rcx, %rcx
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COND_VZEROUPPER
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cmpl %ecx, %edx
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jle L(zero_0)
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subq %rcx, %rax
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ret
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/* Inexpensive place to put this regarding code size / target alignments
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/ ICache NLP. Necessary for 2-byte encoding of jump to page cross
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case which in turn is necessary for hot path (len <= VEC_SIZE) to fit
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in first cache line. */
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L(page_cross):
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movq %rax, %rsi
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andq $-VEC_SIZE, %rsi
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vpcmpeqb (%rsi), %ymm0, %ymm1
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vpmovmskb %ymm1, %ecx
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/* Shift out negative alignment (because we are starting from endptr and
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working backwards). */
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movl %eax, %r8d
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/* notl because eax already has endptr - 1. (-x = ~(x - 1)). */
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notl %r8d
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shlxl %r8d, %ecx, %ecx
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cmpq %rdi, %rsi
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ja L(more_1x_vec)
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lzcntl %ecx, %ecx
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COND_VZEROUPPER
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cmpl %ecx, %edx
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jle L(zero_0)
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subq %rcx, %rax
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ret
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.p2align 4,, 11
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L(ret_vec_x1):
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/* This will naturally add 32 to position. */
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lzcntq %rcx, %rcx
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subq %rcx, %rax
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VZEROUPPER_RETURN
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.p2align 4,, 10
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L(more_2x_vec):
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testl %ecx, %ecx
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jnz L(ret_vec_x0)
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vpcmpeqb -(VEC_SIZE * 2 - 1)(%rax), %ymm0, %ymm1
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vpmovmskb %ymm1, %ecx
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testl %ecx, %ecx
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jnz L(ret_vec_x1)
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/* Needed no matter what. */
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vpcmpeqb -(VEC_SIZE * 3 - 1)(%rax), %ymm0, %ymm1
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vpmovmskb %ymm1, %ecx
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subq $(VEC_SIZE * 4), %rdx
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ja L(more_4x_vec)
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cmpl $(VEC_SIZE * -1), %edx
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jle L(ret_vec_x2_test)
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L(last_vec):
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testl %ecx, %ecx
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jnz L(ret_vec_x2)
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/* Needed no matter what. */
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vpcmpeqb -(VEC_SIZE * 4 - 1)(%rax), %ymm0, %ymm1
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vpmovmskb %ymm1, %ecx
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lzcntl %ecx, %ecx
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subq $(VEC_SIZE * 3), %rax
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COND_VZEROUPPER
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subq %rcx, %rax
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cmpq %rax, %rdi
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ja L(zero_2)
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ret
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/* First in aligning bytes. */
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L(zero_2):
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xorl %eax, %eax
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ret
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.p2align 4,, 4
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L(ret_vec_x2_test):
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lzcntl %ecx, %ecx
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subq $(VEC_SIZE * 2), %rax
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COND_VZEROUPPER
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subq %rcx, %rax
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cmpq %rax, %rdi
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ja L(zero_2)
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ret
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.p2align 4,, 11
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L(ret_vec_x2):
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/* ecx must be non-zero. */
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bsrl %ecx, %ecx
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leaq (VEC_SIZE * -3 + 1)(%rcx, %rax), %rax
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VZEROUPPER_RETURN
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.p2align 4,, 14
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L(ret_vec_x3):
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/* ecx must be non-zero. */
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bsrl %ecx, %ecx
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leaq (VEC_SIZE * -4 + 1)(%rcx, %rax), %rax
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VZEROUPPER_RETURN
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.p2align 4
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L(more_4x_vec):
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testl %ecx, %ecx
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jnz L(ret_vec_x2)
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vpcmpeqb -(VEC_SIZE * 4 - 1)(%rax), %ymm0, %ymm1
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vpmovmskb %ymm1, %ecx
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testl %ecx, %ecx
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jnz L(ret_vec_x3)
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/* Check if near end before re-aligning (otherwise might do an
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unnecissary loop iteration). */
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addq $-(VEC_SIZE * 4), %rax
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cmpq $(VEC_SIZE * 4), %rdx
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jbe L(last_4x_vec)
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/* Align rax to (VEC_SIZE - 1). */
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orq $(VEC_SIZE * 4 - 1), %rax
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movq %rdi, %rdx
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/* Get endptr for loop in rdx. NB: Can't just do while rax > rdi because
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lengths that overflow can be valid and break the comparison. */
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orq $(VEC_SIZE * 4 - 1), %rdx
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.p2align 4
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L(loop_4x_vec):
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/* Need this comparison next no matter what. */
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vpcmpeqb -(VEC_SIZE * 1 - 1)(%rax), %ymm0, %ymm1
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vpcmpeqb -(VEC_SIZE * 2 - 1)(%rax), %ymm0, %ymm2
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vpcmpeqb -(VEC_SIZE * 3 - 1)(%rax), %ymm0, %ymm3
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vpcmpeqb -(VEC_SIZE * 4 - 1)(%rax), %ymm0, %ymm4
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vpor %ymm1, %ymm2, %ymm2
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vpor %ymm3, %ymm4, %ymm4
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vpor %ymm2, %ymm4, %ymm4
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vpmovmskb %ymm4, %esi
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testl %esi, %esi
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jnz L(loop_end)
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addq $(VEC_SIZE * -4), %rax
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cmpq %rdx, %rax
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jne L(loop_4x_vec)
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subl %edi, %edx
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incl %edx
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L(last_4x_vec):
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/* Used no matter what. */
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vpcmpeqb -(VEC_SIZE * 1 - 1)(%rax), %ymm0, %ymm1
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vpmovmskb %ymm1, %ecx
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cmpl $(VEC_SIZE * 2), %edx
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jbe L(last_2x_vec)
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testl %ecx, %ecx
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jnz L(ret_vec_x0_end)
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vpcmpeqb -(VEC_SIZE * 2 - 1)(%rax), %ymm0, %ymm1
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vpmovmskb %ymm1, %ecx
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testl %ecx, %ecx
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jnz L(ret_vec_x1_end)
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/* Used no matter what. */
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vpcmpeqb -(VEC_SIZE * 3 - 1)(%rax), %ymm0, %ymm1
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vpmovmskb %ymm1, %ecx
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cmpl $(VEC_SIZE * 3), %edx
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ja L(last_vec)
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lzcntl %ecx, %ecx
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subq $(VEC_SIZE * 2), %rax
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COND_VZEROUPPER
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subq %rcx, %rax
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cmpq %rax, %rdi
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jbe L(ret0)
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xorl %eax, %eax
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L(ret0):
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ret
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.p2align 4
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L(loop_end):
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vpmovmskb %ymm1, %ecx
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testl %ecx, %ecx
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jnz L(ret_vec_x0_end)
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vpmovmskb %ymm2, %ecx
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testl %ecx, %ecx
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jnz L(ret_vec_x1_end)
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vpmovmskb %ymm3, %ecx
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/* Combine last 2 VEC matches. If ecx (VEC3) is zero (no CHAR in VEC3)
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then it won't affect the result in esi (VEC4). If ecx is non-zero
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then CHAR in VEC3 and bsrq will use that position. */
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salq $32, %rcx
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orq %rsi, %rcx
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bsrq %rcx, %rcx
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leaq (VEC_SIZE * -4 + 1)(%rcx, %rax), %rax
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VZEROUPPER_RETURN
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.p2align 4,, 4
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L(ret_vec_x1_end):
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/* 64-bit version will automatically add 32 (VEC_SIZE). */
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lzcntq %rcx, %rcx
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subq %rcx, %rax
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VZEROUPPER_RETURN
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.p2align 4,, 4
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L(ret_vec_x0_end):
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lzcntl %ecx, %ecx
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subq %rcx, %rax
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VZEROUPPER_RETURN
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/* 2 bytes until next cache line. */
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END(MEMRCHR)
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#endif
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