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ceabdcd130
1. Add default ISA level selection in non-multiarch/rtld
implementations.
2. Add ISA level build guards to different implementations.
- I.e strcmp-avx2.S which is ISA level 3 will only build if
compiled ISA level <= 3. Otherwise there is no reason to
include it as we will always use one of the ISA level 4
implementations (strcmp-evex.S).
3. Refactor the ifunc selector and ifunc implementation list to use
the ISA level aware wrapper macros that allow functions below the
compiled ISA level (with a guranteed replacement) to be skipped.
Tested with and without multiarch on x86_64 for ISA levels:
{generic, x86-64-v2, x86-64-v3, x86-64-v4}
And m32 with and without multiarch.
146 lines
5.2 KiB
C
146 lines
5.2 KiB
C
/* Header defining the minimum x86 ISA level
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Copyright (C) 2022 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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In addition to the permissions in the GNU Lesser General Public
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License, the Free Software Foundation gives you unlimited
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permission to link the compiled version of this file with other
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programs, and to distribute those programs without any restriction
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coming from the use of this file. (The Lesser General Public
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License restrictions do apply in other respects; for example, they
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cover modification of the file, and distribution when not linked
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into another program.)
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<https://www.gnu.org/licenses/>. */
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#ifndef _ISA_LEVEL_H
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#define _ISA_LEVEL_H
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#if defined __SSE__ && defined __SSE2__
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/* NB: ISAs, excluding MMX, in x86-64 ISA level baseline are used. */
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# define __X86_ISA_V1 1
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#else
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# define __X86_ISA_V1 0
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#endif
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#if __X86_ISA_V1 && defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 \
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&& defined HAVE_X86_LAHF_SAHF && defined __POPCNT__ && defined __SSE3__ \
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&& defined __SSSE3__ && defined __SSE4_1__ && defined __SSE4_2__
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/* NB: ISAs in x86-64 ISA level v2 are used. */
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# define __X86_ISA_V2 1
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#else
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# define __X86_ISA_V2 0
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#endif
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#if __X86_ISA_V2 && defined __AVX__ && defined __AVX2__ && defined __F16C__ \
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&& defined __FMA__ && defined __LZCNT__ && defined HAVE_X86_MOVBE \
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&& defined __BMI__ && defined __BMI2__
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/* NB: ISAs in x86-64 ISA level v3 are used. */
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# define __X86_ISA_V3 1
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#else
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# define __X86_ISA_V3 0
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#endif
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#if __X86_ISA_V3 && defined __AVX512F__ && defined __AVX512BW__ \
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&& defined __AVX512CD__ && defined __AVX512DQ__ && defined __AVX512VL__
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/* NB: ISAs in x86-64 ISA level v4 are used. */
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# define __X86_ISA_V4 1
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#else
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# define __X86_ISA_V4 0
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#endif
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#define MINIMUM_X86_ISA_LEVEL \
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(__X86_ISA_V1 + __X86_ISA_V2 + __X86_ISA_V3 + __X86_ISA_V4)
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/* Depending on the minimum ISA level, a feature check result can be a
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compile-time constant.. */
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/* For CPU_FEATURE_USABLE_P. */
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/* ISA level >= 4 guaranteed includes. */
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#define AVX512F_X86_ISA_LEVEL 4
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#define AVX512VL_X86_ISA_LEVEL 4
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#define AVX512BW_X86_ISA_LEVEL 4
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#define AVX512DQ_X86_ISA_LEVEL 4
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/* ISA level >= 3 guaranteed includes. */
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#define AVX_X86_ISA_LEVEL 3
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#define AVX2_X86_ISA_LEVEL 3
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#define BMI2_X86_ISA_LEVEL 3
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#define MOVBE_X86_ISA_LEVEL 3
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/* ISA level >= 2 guaranteed includes. */
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#define SSE4_2_X86_ISA_LEVEL 2
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#define SSE4_1_X86_ISA_LEVEL 2
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#define SSSE3_X86_ISA_LEVEL 2
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/* For X86_ISA_CPU_FEATURES_ARCH_P. */
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/* NB: This feature is enabled when ISA level >= 3, which was disabled
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for the following CPUs:
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- AMD Excavator
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when ISA level < 3. */
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#define AVX_Fast_Unaligned_Load_X86_ISA_LEVEL 3
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/* NB: This feature is disabled when ISA level >= 3, which was enabled
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for the following CPUs:
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- Intel KNL
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when ISA level < 3. */
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#define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3
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/* NB: This feature is disable when ISA level >= 3. All CPUs with
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this feature don't run on glibc built with ISA level >= 3. */
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#define Slow_SSE42_X86_ISA_LEVEL 3
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/* Feature(s) enabled when ISA level >= 2. */
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#define Fast_Unaligned_Load_X86_ISA_LEVEL 2
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/* NB: This feature is disable when ISA level >= 2, which was enabled
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for the early Atom CPUs. */
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#define Slow_BSF_X86_ISA_LEVEL 2
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/* Both X86_ISA_CPU_FEATURE_USABLE_P and X86_ISA_CPU_FEATURES_ARCH_P
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macros are wrappers for the respective CPU_FEATURE{S}_{USABLE|ARCH}_P
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runtime checks. They differ in two ways.
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1. The USABLE_P version is evaluated to true when the feature
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is enabled.
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2. The ARCH_P version has a third argument `not`. The `not`
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argument can either be `!` or empty. If the feature is
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enabled above an ISA level, the third argument should be empty
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and the expression is evaluated to true when the feature is
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enabled. If the feature is disabled above an ISA level, the
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third argument should be `!` and the expression is evaluated
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to true when the feature is disabled.
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*/
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#define X86_ISA_CPU_FEATURE_USABLE_P(ptr, name) \
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(((name##_X86_ISA_LEVEL) <= MINIMUM_X86_ISA_LEVEL) \
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|| CPU_FEATURE_USABLE_P (ptr, name))
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#define X86_ISA_CPU_FEATURES_ARCH_P(ptr, name, not) \
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(((name##_X86_ISA_LEVEL) <= MINIMUM_X86_ISA_LEVEL) \
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|| not CPU_FEATURES_ARCH_P (ptr, name))
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#define ISA_SHOULD_BUILD(isa_build_level) \
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(MINIMUM_X86_ISA_LEVEL <= (isa_build_level) && IS_IN (libc)) \
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|| defined ISA_DEFAULT_IMPL
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#endif
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