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f5ee5362bf
This corresponds to a patch applied to libgcc. In glibc it doesn't actually affect much (only fma, I think). The MIPS sfp-machine.h files have an _FP_CHOOSENAN implementation which emulates hardware semantics of not preserving signaling NaN payloads for an operation with two NaN arguments (although that doesn't suffice to avoid sNaN payload preservation in any case with just one NaN argument). However, those are only hardware semantics in the legacy NaN case; in the NAN2008 case, the architecture documentation says hardware preserves payloads in such cases. Furthermore, this implementation assumes legacy NaN semantics, so in the NAN2008 case the implementation actually has the effect of preserving sNaN payloads but not preserving qNaN payloads, when both should be preserved. This patch fixes the code just to copy from the first argument. Tested for mips64 soft-float. * sysdeps/mips/mips32/sfp-machine.h (_FP_CHOOSENAN): Always preserve NaN payload if [__mips_nan2008]. * sysdeps/mips/mips64/sfp-machine.h (_FP_CHOOSENAN): Likewise.
109 lines
3.0 KiB
C
109 lines
3.0 KiB
C
#include <fenv.h>
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#include <fpu_control.h>
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#define _FP_W_TYPE_SIZE 64
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#define _FP_W_TYPE unsigned long long
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#define _FP_WS_TYPE signed long long
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#define _FP_I_TYPE long long
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#define _FP_MUL_MEAT_S(R,X,Y) \
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_FP_MUL_MEAT_1_imm(_FP_WFRACBITS_S,R,X,Y)
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#define _FP_MUL_MEAT_D(R,X,Y) \
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_FP_MUL_MEAT_1_wide(_FP_WFRACBITS_D,R,X,Y,umul_ppmm)
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#define _FP_MUL_MEAT_Q(R,X,Y) \
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_FP_MUL_MEAT_2_wide_3mul(_FP_WFRACBITS_Q,R,X,Y,umul_ppmm)
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#define _FP_MUL_MEAT_DW_S(R,X,Y) \
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_FP_MUL_MEAT_DW_1_imm(_FP_WFRACBITS_S,R,X,Y)
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#define _FP_MUL_MEAT_DW_D(R,X,Y) \
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_FP_MUL_MEAT_DW_1_wide(_FP_WFRACBITS_D,R,X,Y,umul_ppmm)
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#define _FP_MUL_MEAT_DW_Q(R,X,Y) \
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_FP_MUL_MEAT_DW_2_wide_3mul(_FP_WFRACBITS_Q,R,X,Y,umul_ppmm)
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#define _FP_DIV_MEAT_S(R,X,Y) _FP_DIV_MEAT_1_imm(S,R,X,Y,_FP_DIV_HELP_imm)
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#define _FP_DIV_MEAT_D(R,X,Y) _FP_DIV_MEAT_1_udiv_norm(D,R,X,Y)
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#define _FP_DIV_MEAT_Q(R,X,Y) _FP_DIV_MEAT_2_udiv(Q,R,X,Y)
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#ifdef __mips_nan2008
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# define _FP_NANFRAC_S ((_FP_QNANBIT_S << 1) - 1)
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# define _FP_NANFRAC_D ((_FP_QNANBIT_D << 1) - 1)
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# define _FP_NANFRAC_Q ((_FP_QNANBIT_Q << 1) - 1), -1
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#else
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# define _FP_NANFRAC_S (_FP_QNANBIT_S - 1)
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# define _FP_NANFRAC_D (_FP_QNANBIT_D - 1)
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# define _FP_NANFRAC_Q (_FP_QNANBIT_Q - 1), -1
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#endif
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#define _FP_NANSIGN_S 0
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#define _FP_NANSIGN_D 0
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#define _FP_NANSIGN_Q 0
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#define _FP_KEEPNANFRACP 1
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#ifdef __mips_nan2008
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# define _FP_QNANNEGATEDP 0
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#else
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# define _FP_QNANNEGATEDP 1
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#endif
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#ifdef __mips_nan2008
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/* NaN payloads should be preserved for NAN2008. */
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# define _FP_CHOOSENAN(fs, wc, R, X, Y, OP) \
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do \
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{ \
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R##_s = X##_s; \
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_FP_FRAC_COPY_##wc (R, X); \
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R##_c = FP_CLS_NAN; \
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} \
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while (0)
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#else
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/* From my experiments it seems X is chosen unless one of the
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NaNs is sNaN, in which case the result is NANSIGN/NANFRAC. */
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# define _FP_CHOOSENAN(fs, wc, R, X, Y, OP) \
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do { \
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if ((_FP_FRAC_HIGH_RAW_##fs(X) | \
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_FP_FRAC_HIGH_RAW_##fs(Y)) & _FP_QNANBIT_##fs) \
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{ \
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R##_s = _FP_NANSIGN_##fs; \
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_FP_FRAC_SET_##wc(R,_FP_NANFRAC_##fs); \
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} \
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else \
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{ \
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R##_s = X##_s; \
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_FP_FRAC_COPY_##wc(R,X); \
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} \
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R##_c = FP_CLS_NAN; \
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} while (0)
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#endif
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#define _FP_DECL_EX fpu_control_t _fcw
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#define FP_ROUNDMODE (_fcw & 0x3)
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#define FP_RND_NEAREST FE_TONEAREST
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#define FP_RND_ZERO FE_TOWARDZERO
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#define FP_RND_PINF FE_UPWARD
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#define FP_RND_MINF FE_DOWNWARD
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#define FP_EX_INVALID FE_INVALID
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#define FP_EX_OVERFLOW FE_OVERFLOW
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#define FP_EX_UNDERFLOW FE_UNDERFLOW
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#define FP_EX_DIVZERO FE_DIVBYZERO
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#define FP_EX_INEXACT FE_INEXACT
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#define _FP_TININESS_AFTER_ROUNDING 1
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#ifdef __mips_hard_float
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#define FP_INIT_ROUNDMODE \
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do { \
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_FPU_GETCW (_fcw); \
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} while (0)
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#define FP_HANDLE_EXCEPTIONS \
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do { \
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if (__builtin_expect (_fex, 0)) \
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_FPU_SETCW (_fcw | _fex | (_fex << 10)); \
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} while (0)
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#define FP_TRAPPING_EXCEPTIONS ((_fcw >> 5) & 0x7c)
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#else
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#define FP_INIT_ROUNDMODE _fcw = FP_RND_NEAREST
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#endif
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