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https://sourceware.org/git/glibc.git
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5a82c74822
Also, change sources.redhat.com to sourceware.org.
This patch was automatically generated by running the following shell
script, which uses GNU sed, and which avoids modifying files imported
from upstream:
sed -ri '
s,(http|ftp)(://(.*\.)?(gnu|fsf|sourceware)\.org($|[^.]|\.[^a-z])),https\2,g
s,(http|ftp)(://(.*\.)?)sources\.redhat\.com($|[^.]|\.[^a-z]),https\2sourceware.org\4,g
' \
$(find $(git ls-files) -prune -type f \
! -name '*.po' \
! -name 'ChangeLog*' \
! -path COPYING ! -path COPYING.LIB \
! -path manual/fdl-1.3.texi ! -path manual/lgpl-2.1.texi \
! -path manual/texinfo.tex ! -path scripts/config.guess \
! -path scripts/config.sub ! -path scripts/install-sh \
! -path scripts/mkinstalldirs ! -path scripts/move-if-change \
! -path INSTALL ! -path locale/programs/charmap-kw.h \
! -path po/libc.pot ! -path sysdeps/gnu/errlist.c \
! '(' -name configure \
-execdir test -f configure.ac -o -f configure.in ';' ')' \
! '(' -name preconfigure \
-execdir test -f preconfigure.ac ';' ')' \
-print)
and then by running 'make dist-prepare' to regenerate files built
from the altered files, and then executing the following to cleanup:
chmod a+x sysdeps/unix/sysv/linux/riscv/configure
# Omit irrelevant whitespace and comment-only changes,
# perhaps from a slightly-different Autoconf version.
git checkout -f \
sysdeps/csky/configure \
sysdeps/hppa/configure \
sysdeps/riscv/configure \
sysdeps/unix/sysv/linux/csky/configure
# Omit changes that caused a pre-commit check to fail like this:
# remote: *** error: sysdeps/powerpc/powerpc64/ppc-mcount.S: trailing lines
git checkout -f \
sysdeps/powerpc/powerpc64/ppc-mcount.S \
sysdeps/unix/sysv/linux/s390/s390-64/syscall.S
# Omit change that caused a pre-commit check to fail like this:
# remote: *** error: sysdeps/sparc/sparc64/multiarch/memcpy-ultra3.S: last line does not end in newline
git checkout -f sysdeps/sparc/sparc64/multiarch/memcpy-ultra3.S
333 lines
8.2 KiB
ArmAsm
333 lines
8.2 KiB
ArmAsm
/* Copy SIZE bytes from SRC to DEST. For SUN4V Niagara-4.
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Copyright (C) 2012-2019 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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Contributed by David S. Miller (davem@davemloft.net)
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<https://www.gnu.org/licenses/>. */
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#include <sysdep.h>
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#define ASI_BLK_INIT_QUAD_LDD_P 0xe2
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#define FPRS_FEF 0x04
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/* On T4 it is very expensive to access ASRs like %fprs and
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* %asi, avoiding a read or a write can save ~50 cycles.
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*/
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#define FPU_ENTER \
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rd %fprs, %o5; \
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andcc %o5, FPRS_FEF, %g0; \
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be,a,pn %icc, 999f; \
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wr %g0, FPRS_FEF, %fprs; \
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999:
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#define VISEntryHalf FPU_ENTER
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#define VISExitHalf and %o5, FPRS_FEF, %o5; wr %o5, 0x0, %fprs
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#define GLOBAL_SPARE %g5
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#define STORE_ASI ASI_BLK_INIT_QUAD_LDD_P
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#define EX_LD(x) x
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#define EX_ST(x) x
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#define EX_RETVAL(x) x
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#define LOAD(type,addr,dest) type [addr], dest
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#define STORE(type,src,addr) type src, [addr]
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#define STORE_INIT(src,addr) stxa src, [addr] STORE_ASI
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#if IS_IN (libc)
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.register %g2,#scratch
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.register %g3,#scratch
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.register %g6,#scratch
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.text
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ENTRY(__mempcpy_niagara4)
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ba,pt %icc, 101f
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add %o0, %o2, %o3
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END(__mempcpy_niagara4)
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.align 32
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ENTRY(__memcpy_niagara4)
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100: /* %o0=dst, %o1=src, %o2=len */
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mov %o0, %o3
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101:
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#ifndef __arch64__
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srl %o2, 0, %o2
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#endif
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brz,pn %o2, .Lexit
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cmp %o2, 3
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ble,pn %icc, .Ltiny
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cmp %o2, 19
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ble,pn %icc, .Lsmall
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or %o0, %o1, %g2
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cmp %o2, 128
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bl,pn %icc, .Lmedium
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nop
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.Llarge:/* len >= 0x80 */
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/* First get dest 8 byte aligned. */
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sub %g0, %o0, %g1
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and %g1, 0x7, %g1
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brz,pt %g1, 51f
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sub %o2, %g1, %o2
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1: EX_LD(LOAD(ldub, %o1 + 0x00, %g2))
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add %o1, 1, %o1
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subcc %g1, 1, %g1
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add %o0, 1, %o0
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bne,pt %icc, 1b
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EX_ST(STORE(stb, %g2, %o0 - 0x01))
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51: LOAD(prefetch, %o1 + 0x040, #n_reads_strong)
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LOAD(prefetch, %o1 + 0x080, #n_reads_strong)
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LOAD(prefetch, %o1 + 0x0c0, #n_reads_strong)
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LOAD(prefetch, %o1 + 0x100, #n_reads_strong)
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LOAD(prefetch, %o1 + 0x140, #n_reads_strong)
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LOAD(prefetch, %o1 + 0x180, #n_reads_strong)
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LOAD(prefetch, %o1 + 0x1c0, #n_reads_strong)
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LOAD(prefetch, %o1 + 0x200, #n_reads_strong)
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/* Check if we can use the straight fully aligned
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* loop, or we require the alignaddr/faligndata variant.
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*/
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andcc %o1, 0x7, %o5
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bne,pn %icc, .Llarge_src_unaligned
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sub %g0, %o0, %g1
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/* Legitimize the use of initializing stores by getting dest
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* to be 64-byte aligned.
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*/
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and %g1, 0x3f, %g1
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brz,pt %g1, .Llarge_aligned
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sub %o2, %g1, %o2
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1: EX_LD(LOAD(ldx, %o1 + 0x00, %g2))
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add %o1, 8, %o1
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subcc %g1, 8, %g1
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add %o0, 8, %o0
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bne,pt %icc, 1b
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EX_ST(STORE(stx, %g2, %o0 - 0x08))
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.Llarge_aligned:
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/* len >= 0x80 && src 8-byte aligned && dest 8-byte aligned */
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andn %o2, 0x3f, %o4
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sub %o2, %o4, %o2
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1: EX_LD(LOAD(ldx, %o1 + 0x00, %g1))
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add %o1, 0x40, %o1
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EX_LD(LOAD(ldx, %o1 - 0x38, %g2))
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subcc %o4, 0x40, %o4
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EX_LD(LOAD(ldx, %o1 - 0x30, %g3))
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EX_LD(LOAD(ldx, %o1 - 0x28, GLOBAL_SPARE))
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EX_LD(LOAD(ldx, %o1 - 0x20, %o5))
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EX_ST(STORE_INIT(%g1, %o0))
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add %o0, 0x08, %o0
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EX_ST(STORE_INIT(%g2, %o0))
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add %o0, 0x08, %o0
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EX_LD(LOAD(ldx, %o1 - 0x18, %g2))
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EX_ST(STORE_INIT(%g3, %o0))
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add %o0, 0x08, %o0
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EX_LD(LOAD(ldx, %o1 - 0x10, %g3))
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EX_ST(STORE_INIT(GLOBAL_SPARE, %o0))
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add %o0, 0x08, %o0
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EX_LD(LOAD(ldx, %o1 - 0x08, GLOBAL_SPARE))
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EX_ST(STORE_INIT(%o5, %o0))
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add %o0, 0x08, %o0
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EX_ST(STORE_INIT(%g2, %o0))
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add %o0, 0x08, %o0
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EX_ST(STORE_INIT(%g3, %o0))
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add %o0, 0x08, %o0
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EX_ST(STORE_INIT(GLOBAL_SPARE, %o0))
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add %o0, 0x08, %o0
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bne,pt %icc, 1b
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LOAD(prefetch, %o1 + 0x200, #n_reads_strong)
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membar #StoreLoad | #StoreStore
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brz,pn %o2, .Lexit
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cmp %o2, 19
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ble,pn %icc, .Lsmall_unaligned
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nop
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ba,a,pt %icc, .Lmedium_noprefetch
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.Lexit: retl
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mov EX_RETVAL(%o3), %o0
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.Llarge_src_unaligned:
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andn %o2, 0x3f, %o4
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sub %o2, %o4, %o2
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VISEntryHalf
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alignaddr %o1, %g0, %g1
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add %o1, %o4, %o1
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EX_LD(LOAD(ldd, %g1 + 0x00, %f0))
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1: EX_LD(LOAD(ldd, %g1 + 0x08, %f2))
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subcc %o4, 0x40, %o4
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EX_LD(LOAD(ldd, %g1 + 0x10, %f4))
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EX_LD(LOAD(ldd, %g1 + 0x18, %f6))
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EX_LD(LOAD(ldd, %g1 + 0x20, %f8))
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EX_LD(LOAD(ldd, %g1 + 0x28, %f10))
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EX_LD(LOAD(ldd, %g1 + 0x30, %f12))
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EX_LD(LOAD(ldd, %g1 + 0x38, %f14))
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faligndata %f0, %f2, %f16
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EX_LD(LOAD(ldd, %g1 + 0x40, %f0))
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faligndata %f2, %f4, %f18
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add %g1, 0x40, %g1
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faligndata %f4, %f6, %f20
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faligndata %f6, %f8, %f22
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faligndata %f8, %f10, %f24
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faligndata %f10, %f12, %f26
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faligndata %f12, %f14, %f28
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faligndata %f14, %f0, %f30
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EX_ST(STORE(std, %f16, %o0 + 0x00))
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EX_ST(STORE(std, %f18, %o0 + 0x08))
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EX_ST(STORE(std, %f20, %o0 + 0x10))
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EX_ST(STORE(std, %f22, %o0 + 0x18))
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EX_ST(STORE(std, %f24, %o0 + 0x20))
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EX_ST(STORE(std, %f26, %o0 + 0x28))
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EX_ST(STORE(std, %f28, %o0 + 0x30))
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EX_ST(STORE(std, %f30, %o0 + 0x38))
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add %o0, 0x40, %o0
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bne,pt %icc, 1b
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LOAD(prefetch, %g1 + 0x200, #n_reads_strong)
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VISExitHalf
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brz,pn %o2, .Lexit
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cmp %o2, 19
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ble,pn %icc, .Lsmall_unaligned
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nop
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ba,a,pt %icc, .Lmedium_unaligned
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.Lmedium:
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LOAD(prefetch, %o1 + 0x40, #n_reads_strong)
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andcc %g2, 0x7, %g0
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bne,pn %icc, .Lmedium_unaligned
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nop
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.Lmedium_noprefetch:
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andncc %o2, 0x20 - 1, %o5
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be,pn %icc, 2f
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sub %o2, %o5, %o2
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1: EX_LD(LOAD(ldx, %o1 + 0x00, %g1))
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EX_LD(LOAD(ldx, %o1 + 0x08, %g2))
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EX_LD(LOAD(ldx, %o1 + 0x10, GLOBAL_SPARE))
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EX_LD(LOAD(ldx, %o1 + 0x18, %o4))
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add %o1, 0x20, %o1
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subcc %o5, 0x20, %o5
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EX_ST(STORE(stx, %g1, %o0 + 0x00))
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EX_ST(STORE(stx, %g2, %o0 + 0x08))
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EX_ST(STORE(stx, GLOBAL_SPARE, %o0 + 0x10))
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EX_ST(STORE(stx, %o4, %o0 + 0x18))
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bne,pt %icc, 1b
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add %o0, 0x20, %o0
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2: andcc %o2, 0x18, %o5
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be,pt %icc, 3f
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sub %o2, %o5, %o2
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1: EX_LD(LOAD(ldx, %o1 + 0x00, %g1))
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add %o1, 0x08, %o1
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add %o0, 0x08, %o0
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subcc %o5, 0x08, %o5
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bne,pt %icc, 1b
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EX_ST(STORE(stx, %g1, %o0 - 0x08))
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3: brz,pt %o2, .Lexit
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cmp %o2, 0x04
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bl,pn %icc, .Ltiny
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nop
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EX_LD(LOAD(lduw, %o1 + 0x00, %g1))
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add %o1, 0x04, %o1
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add %o0, 0x04, %o0
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subcc %o2, 0x04, %o2
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bne,pn %icc, .Ltiny
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EX_ST(STORE(stw, %g1, %o0 - 0x04))
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ba,a,pt %icc, .Lexit
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.Lmedium_unaligned:
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/* First get dest 8 byte aligned. */
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sub %g0, %o0, %g1
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and %g1, 0x7, %g1
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brz,pt %g1, 2f
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sub %o2, %g1, %o2
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1: EX_LD(LOAD(ldub, %o1 + 0x00, %g2))
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add %o1, 1, %o1
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subcc %g1, 1, %g1
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add %o0, 1, %o0
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bne,pt %icc, 1b
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EX_ST(STORE(stb, %g2, %o0 - 0x01))
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2:
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and %o1, 0x7, %g1
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brz,pn %g1, .Lmedium_noprefetch
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sll %g1, 3, %g1
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mov 64, %g2
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sub %g2, %g1, %g2
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andn %o1, 0x7, %o1
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EX_LD(LOAD(ldx, %o1 + 0x00, %o4))
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sllx %o4, %g1, %o4
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andn %o2, 0x08 - 1, %o5
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sub %o2, %o5, %o2
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1: EX_LD(LOAD(ldx, %o1 + 0x08, %g3))
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add %o1, 0x08, %o1
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subcc %o5, 0x08, %o5
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srlx %g3, %g2, GLOBAL_SPARE
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or GLOBAL_SPARE, %o4, GLOBAL_SPARE
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EX_ST(STORE(stx, GLOBAL_SPARE, %o0 + 0x00))
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add %o0, 0x08, %o0
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bne,pt %icc, 1b
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sllx %g3, %g1, %o4
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srl %g1, 3, %g1
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add %o1, %g1, %o1
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brz,pn %o2, .Lexit
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nop
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ba,pt %icc, .Lsmall_unaligned
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.Ltiny:
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EX_LD(LOAD(ldub, %o1 + 0x00, %g1))
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subcc %o2, 1, %o2
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be,pn %icc, .Lexit
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EX_ST(STORE(stb, %g1, %o0 + 0x00))
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EX_LD(LOAD(ldub, %o1 + 0x01, %g1))
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subcc %o2, 1, %o2
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be,pn %icc, .Lexit
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EX_ST(STORE(stb, %g1, %o0 + 0x01))
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EX_LD(LOAD(ldub, %o1 + 0x02, %g1))
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ba,pt %icc, .Lexit
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EX_ST(STORE(stb, %g1, %o0 + 0x02))
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.Lsmall:
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andcc %g2, 0x3, %g0
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bne,pn %icc, .Lsmall_unaligned
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andn %o2, 0x4 - 1, %o5
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sub %o2, %o5, %o2
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1:
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EX_LD(LOAD(lduw, %o1 + 0x00, %g1))
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add %o1, 0x04, %o1
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subcc %o5, 0x04, %o5
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add %o0, 0x04, %o0
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bne,pt %icc, 1b
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EX_ST(STORE(stw, %g1, %o0 - 0x04))
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brz,pt %o2, .Lexit
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nop
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ba,a,pt %icc, .Ltiny
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.Lsmall_unaligned:
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1: EX_LD(LOAD(ldub, %o1 + 0x00, %g1))
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add %o1, 1, %o1
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add %o0, 1, %o0
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subcc %o2, 1, %o2
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bne,pt %icc, 1b
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EX_ST(STORE(stb, %g1, %o0 - 0x01))
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ba,a,pt %icc, .Lexit
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END(__memcpy_niagara4)
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#endif
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