H.J. Lu f53ffc9b90 x86: Handle _SC_LEVEL1_ICACHE_LINESIZE [BZ #27444] ... commit 2d651eb926 Author: H.J. Lu <hjl.tools@gmail.com> Date: Fri Sep 18 07:55:14 2020 -0700 x86: Move x86 processor cache info to cpu_features missed _SC_LEVEL1_ICACHE_LINESIZE. 1. Add level1_icache_linesize to struct cpu_features. 2. Initialize level1_icache_linesize by calling handle_intel, handle_zhaoxin and handle_amd with _SC_LEVEL1_ICACHE_LINESIZE. 3. Return level1_icache_linesize for _SC_LEVEL1_ICACHE_LINESIZE. Reviewed-by: Carlos O'Donell <carlos@redhat.com>		2021-03-15 05:43:26 -07:00
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cpu-features-preferred_feature_index_1.def	x86: Automate generation of PREFERRED_FEATURE_INDEX_1 bitfield	2021-03-02 15:01:06 +01:00
cpu-features.h	x86: Handle _SC_LEVEL1_ICACHE_LINESIZE [BZ #27444]	2021-03-15 05:43:26 -07:00