mirror of
https://sourceware.org/git/glibc.git
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cd080d0741
This commit doesn't affect libc.so.6, its just housekeeping to prepare for adding explicit ISA level support. Tested build on x86_64 and x86_32 with/without multiarch.
188 lines
3.9 KiB
ArmAsm
188 lines
3.9 KiB
ArmAsm
/* strchr optimized with SSE2.
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Copyright (C) 2009-2022 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<https://www.gnu.org/licenses/>. */
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#if IS_IN (libc) || defined STRCHR
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# ifndef STRCHR
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# define STRCHR __strchr_sse2
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# endif
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# include <sysdep.h>
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.text
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ENTRY (STRCHR)
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movd %esi, %xmm1
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movl %edi, %eax
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andl $4095, %eax
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punpcklbw %xmm1, %xmm1
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cmpl $4032, %eax
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punpcklwd %xmm1, %xmm1
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pshufd $0, %xmm1, %xmm1
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jg L(cross_page)
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movdqu (%rdi), %xmm0
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pxor %xmm3, %xmm3
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movdqa %xmm0, %xmm4
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pcmpeqb %xmm1, %xmm0
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pcmpeqb %xmm3, %xmm4
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por %xmm4, %xmm0
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pmovmskb %xmm0, %eax
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test %eax, %eax
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je L(next_48_bytes)
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bsf %eax, %eax
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# ifdef AS_STRCHRNUL
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leaq (%rdi,%rax), %rax
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# else
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movl $0, %edx
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leaq (%rdi,%rax), %rax
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cmpb %sil, (%rax)
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cmovne %rdx, %rax
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# endif
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ret
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.p2align 3
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L(next_48_bytes):
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movdqu 16(%rdi), %xmm0
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movdqa %xmm0, %xmm4
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pcmpeqb %xmm1, %xmm0
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pcmpeqb %xmm3, %xmm4
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por %xmm4, %xmm0
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pmovmskb %xmm0, %ecx
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movdqu 32(%rdi), %xmm0
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movdqa %xmm0, %xmm4
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pcmpeqb %xmm1, %xmm0
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salq $16, %rcx
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pcmpeqb %xmm3, %xmm4
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por %xmm4, %xmm0
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pmovmskb %xmm0, %eax
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movdqu 48(%rdi), %xmm0
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pcmpeqb %xmm0, %xmm3
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salq $32, %rax
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pcmpeqb %xmm1, %xmm0
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orq %rcx, %rax
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por %xmm3, %xmm0
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pmovmskb %xmm0, %ecx
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salq $48, %rcx
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orq %rcx, %rax
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testq %rax, %rax
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jne L(return)
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L(loop_start):
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/* We use this alignment to force loop be aligned to 8 but not
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16 bytes. This gives better sheduling on AMD processors. */
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.p2align 4
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pxor %xmm6, %xmm6
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andq $-64, %rdi
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.p2align 3
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L(loop64):
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addq $64, %rdi
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movdqa (%rdi), %xmm5
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movdqa 16(%rdi), %xmm2
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movdqa 32(%rdi), %xmm3
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pxor %xmm1, %xmm5
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movdqa 48(%rdi), %xmm4
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pxor %xmm1, %xmm2
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pxor %xmm1, %xmm3
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pminub (%rdi), %xmm5
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pxor %xmm1, %xmm4
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pminub 16(%rdi), %xmm2
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pminub 32(%rdi), %xmm3
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pminub %xmm2, %xmm5
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pminub 48(%rdi), %xmm4
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pminub %xmm3, %xmm5
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pminub %xmm4, %xmm5
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pcmpeqb %xmm6, %xmm5
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pmovmskb %xmm5, %eax
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testl %eax, %eax
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je L(loop64)
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movdqa (%rdi), %xmm5
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movdqa %xmm5, %xmm0
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pcmpeqb %xmm1, %xmm5
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pcmpeqb %xmm6, %xmm0
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por %xmm0, %xmm5
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pcmpeqb %xmm6, %xmm2
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pcmpeqb %xmm6, %xmm3
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pcmpeqb %xmm6, %xmm4
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pmovmskb %xmm5, %ecx
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pmovmskb %xmm2, %eax
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salq $16, %rax
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pmovmskb %xmm3, %r8d
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pmovmskb %xmm4, %edx
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salq $32, %r8
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orq %r8, %rax
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orq %rcx, %rax
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salq $48, %rdx
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orq %rdx, %rax
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.p2align 3
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L(return):
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bsfq %rax, %rax
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# ifdef AS_STRCHRNUL
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leaq (%rdi,%rax), %rax
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# else
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movl $0, %edx
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leaq (%rdi,%rax), %rax
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cmpb %sil, (%rax)
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cmovne %rdx, %rax
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# endif
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ret
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.p2align 4
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L(cross_page):
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movq %rdi, %rdx
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pxor %xmm2, %xmm2
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andq $-64, %rdx
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movdqa %xmm1, %xmm0
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movdqa (%rdx), %xmm3
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movdqa %xmm3, %xmm4
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pcmpeqb %xmm1, %xmm3
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pcmpeqb %xmm2, %xmm4
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por %xmm4, %xmm3
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pmovmskb %xmm3, %r8d
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movdqa 16(%rdx), %xmm3
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movdqa %xmm3, %xmm4
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pcmpeqb %xmm1, %xmm3
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pcmpeqb %xmm2, %xmm4
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por %xmm4, %xmm3
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pmovmskb %xmm3, %eax
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movdqa 32(%rdx), %xmm3
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movdqa %xmm3, %xmm4
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pcmpeqb %xmm1, %xmm3
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salq $16, %rax
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pcmpeqb %xmm2, %xmm4
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por %xmm4, %xmm3
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pmovmskb %xmm3, %r9d
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movdqa 48(%rdx), %xmm3
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pcmpeqb %xmm3, %xmm2
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salq $32, %r9
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pcmpeqb %xmm3, %xmm0
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orq %r9, %rax
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orq %r8, %rax
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por %xmm2, %xmm0
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pmovmskb %xmm0, %ecx
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salq $48, %rcx
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orq %rcx, %rax
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movl %edi, %ecx
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subb %dl, %cl
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shrq %cl, %rax
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testq %rax, %rax
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jne L(return)
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jmp L(loop_start)
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END (STRCHR)
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#endif
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