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297 lines
8.2 KiB
ArmAsm
297 lines
8.2 KiB
ArmAsm
/* __memcmpeq optimized with EVEX.
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Copyright (C) 2017-2024 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<https://www.gnu.org/licenses/>. */
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#include <isa-level.h>
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#if ISA_SHOULD_BUILD (4)
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/* __memcmpeq is implemented as:
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1. Use ymm vector compares when possible. The only case where
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vector compares is not possible for when size < VEC_SIZE
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and loading from either s1 or s2 would cause a page cross.
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2. Use xmm vector compare when size >= 8 bytes.
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3. Optimistically compare up to first 4 * VEC_SIZE one at a
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to check for early mismatches. Only do this if its guaranteed the
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work is not wasted.
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4. If size is 8 * VEC_SIZE or less, unroll the loop.
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5. Compare 4 * VEC_SIZE at a time with the aligned first memory
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area.
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6. Use 2 vector compares when size is 2 * VEC_SIZE or less.
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7. Use 4 vector compares when size is 4 * VEC_SIZE or less.
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8. Use 8 vector compares when size is 8 * VEC_SIZE or less. */
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# include <sysdep.h>
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# ifndef MEMCMPEQ
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# define MEMCMPEQ __memcmpeq_evex
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# endif
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# ifndef VEC_SIZE
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# include "x86-evex256-vecs.h"
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# endif
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# include "reg-macros.h"
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# if VEC_SIZE == 32
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# define TEST_ZERO_VCMP(reg) inc %VGPR(reg)
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# define TEST_ZERO(reg) test %VGPR(reg), %VGPR(reg)
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# define TO_32BIT_P1(reg) /* Do nothing. */
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# define TO_32BIT_P2(reg) /* Do nothing. */
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# define TO_32BIT(reg) /* Do nothing. */
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# define VEC_CMP VPCMPEQ
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# elif VEC_SIZE == 64
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# define TEST_ZERO_VCMP(reg) TEST_ZERO(reg)
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# define TEST_ZERO(reg) neg %VGPR(reg)
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/* VEC_SIZE == 64 needs to reduce the 64-bit mask to a 32-bit
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int. We have two methods for this. If the mask with branched
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on, we use `neg` for the branch then `sbb` to get the 32-bit
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return. If the mask was no branched on, we just use
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`popcntq`. */
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# define TO_32BIT_P1(reg) TEST_ZERO(reg)
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# define TO_32BIT_P2(reg) sbb %VGPR_SZ(reg, 32), %VGPR_SZ(reg, 32)
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# define TO_32BIT(reg) popcntq %reg, %reg
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# define VEC_CMP VPCMPNEQ
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# else
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# error "Unsupported VEC_SIZE"
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# endif
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# define VMOVU_MASK vmovdqu8
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# define VPCMPNEQ vpcmpneqb
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# define VPCMPEQ vpcmpeqb
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# define VPTEST vptestmb
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# define PAGE_SIZE 4096
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.section SECTION(.text), "ax", @progbits
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ENTRY_P2ALIGN (MEMCMPEQ, 6)
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# ifdef __ILP32__
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/* Clear the upper 32 bits. */
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movl %edx, %edx
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# endif
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cmp $VEC_SIZE, %RDX_LP
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/* Fall through for [0, VEC_SIZE] as its the hottest. */
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ja L(more_1x_vec)
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/* Create mask of bytes that are guaranteed to be valid because
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of length (edx). Using masked movs allows us to skip checks
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for page crosses/zero size. */
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mov $-1, %VRAX
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bzhi %VRDX, %VRAX, %VRAX
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/* NB: A `jz` might be useful here. Page-faults that are
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invalidated by predicate execution (the evex mask) can be
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very slow. The expectation is this is not the norm so and
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"most" code will not regularly call 'memcmp' with length = 0
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and memory that is not wired up. */
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KMOV %VRAX, %k2
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/* Use masked loads as VEC_SIZE could page cross where length
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(edx) would not. */
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VMOVU_MASK (%rsi), %VMM(2){%k2}{z}
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VPCMPNEQ (%rdi), %VMM(2), %k1{%k2}
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KMOV %k1, %VRAX
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TO_32BIT (VRAX)
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ret
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.p2align 4,, 3
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L(last_1x_vec):
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VMOVU -(VEC_SIZE * 1)(%rsi, %rdx), %VMM(1)
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VPCMPNEQ -(VEC_SIZE * 1)(%rdi, %rdx), %VMM(1), %k1
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KMOV %k1, %VRAX
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TO_32BIT_P1 (rax)
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L(return_neq0):
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TO_32BIT_P2 (rax)
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ret
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.p2align 4,, 12
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L(more_1x_vec):
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/* From VEC + 1 to 2 * VEC. */
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VMOVU (%rsi), %VMM(1)
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/* Use compare not equals to directly check for mismatch. */
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VPCMPNEQ (%rdi), %VMM(1), %k1
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KMOV %k1, %VRAX
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TEST_ZERO (rax)
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jnz L(return_neq0)
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cmpq $(VEC_SIZE * 2), %rdx
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jbe L(last_1x_vec)
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/* Check second VEC no matter what. */
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VMOVU VEC_SIZE(%rsi), %VMM(2)
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VPCMPNEQ VEC_SIZE(%rdi), %VMM(2), %k1
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KMOV %k1, %VRAX
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TEST_ZERO (rax)
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jnz L(return_neq0)
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/* Less than 4 * VEC. */
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cmpq $(VEC_SIZE * 4), %rdx
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jbe L(last_2x_vec)
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/* Check third and fourth VEC no matter what. */
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VMOVU (VEC_SIZE * 2)(%rsi), %VMM(3)
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VEC_CMP (VEC_SIZE * 2)(%rdi), %VMM(3), %k1
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KMOV %k1, %VRAX
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TEST_ZERO_VCMP (rax)
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jnz L(return_neq0)
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VMOVU (VEC_SIZE * 3)(%rsi), %VMM(4)
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VEC_CMP (VEC_SIZE * 3)(%rdi), %VMM(4), %k1
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KMOV %k1, %VRAX
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TEST_ZERO_VCMP (rax)
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jnz L(return_neq0)
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/* Go to 4x VEC loop. */
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cmpq $(VEC_SIZE * 8), %rdx
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ja L(more_8x_vec)
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/* Handle remainder of size = 4 * VEC + 1 to 8 * VEC without any
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branches. */
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VMOVU -(VEC_SIZE * 1)(%rsi, %rdx), %VMM(1)
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VMOVU -(VEC_SIZE * 2)(%rsi, %rdx), %VMM(2)
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addq %rdx, %rdi
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/* Wait to load from s1 until addressed adjust due to
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unlamination. */
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/* vpxor will be all 0s if s1 and s2 are equal. Otherwise it
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will have some 1s. */
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vpxorq -(VEC_SIZE * 1)(%rdi), %VMM(1), %VMM(1)
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/* Ternary logic to xor -(VEC_SIZE * 3)(%rdi) with VEC(2) while
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oring with VEC(1). Result is stored in VEC(1). */
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vpternlogd $0xde, -(VEC_SIZE * 2)(%rdi), %VMM(1), %VMM(2)
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cmpl $(VEC_SIZE * 6), %edx
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jbe L(4x_last_2x_vec)
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VMOVU -(VEC_SIZE * 3)(%rsi, %rdx), %VMM(3)
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vpxorq -(VEC_SIZE * 3)(%rdi), %VMM(3), %VMM(3)
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/* Or together VEC(1), VEC(2), and VEC(3) into VEC(3). */
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VMOVU -(VEC_SIZE * 4)(%rsi, %rdx), %VMM(4)
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vpxorq -(VEC_SIZE * 4)(%rdi), %VMM(4), %VMM(4)
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/* Or together VEC(4), VEC(3), and VEC(2) into VEC(2). */
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vpternlogd $0xfe, %VMM(4), %VMM(3), %VMM(2)
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/* Compare VEC(4) with 0. If any 1s s1 and s2 don't match. */
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L(4x_last_2x_vec):
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VPTEST %VMM(2), %VMM(2), %k1
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KMOV %k1, %VRAX
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TO_32BIT (VRAX)
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ret
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.p2align 4,, 10
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L(more_8x_vec):
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/* Set end of s1 in rdx. */
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leaq -(VEC_SIZE * 4)(%rdi, %rdx), %rdx
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/* rsi stores s2 - s1. This allows loop to only update one
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pointer. */
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subq %rdi, %rsi
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/* Align s1 pointer. */
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andq $-VEC_SIZE, %rdi
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/* Adjust because first 4x vec where check already. */
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subq $-(VEC_SIZE * 4), %rdi
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.p2align 5,, 12
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.p2align 4,, 8
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L(loop_4x_vec):
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VMOVU (%rsi, %rdi), %VMM(1)
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vpxorq (%rdi), %VMM(1), %VMM(1)
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VMOVU VEC_SIZE(%rsi, %rdi), %VMM(2)
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vpternlogd $0xde, (VEC_SIZE)(%rdi), %VMM(1), %VMM(2)
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VMOVU (VEC_SIZE * 2)(%rsi, %rdi), %VMM(3)
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vpxorq (VEC_SIZE * 2)(%rdi), %VMM(3), %VMM(3)
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VMOVU (VEC_SIZE * 3)(%rsi, %rdi), %VMM(4)
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vpxorq (VEC_SIZE * 3)(%rdi), %VMM(4), %VMM(4)
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vpternlogd $0xfe, %VMM(2), %VMM(3), %VMM(4)
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VPTEST %VMM(4), %VMM(4), %k1
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KMOV %k1, %VRAX
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TEST_ZERO (rax)
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jnz L(return_neq2)
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subq $-(VEC_SIZE * 4), %rdi
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cmpq %rdx, %rdi
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jb L(loop_4x_vec)
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subq %rdx, %rdi
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VMOVU (VEC_SIZE * 3)(%rsi, %rdx), %VMM(4)
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vpxorq (VEC_SIZE * 3)(%rdx), %VMM(4), %VMM(4)
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/* rdi has 4 * VEC_SIZE - remaining length. */
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/* Load regardless of branch. */
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VMOVU (VEC_SIZE * 2)(%rsi, %rdx), %VMM(3)
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/* Ternary logic to xor (VEC_SIZE * 2)(%rdx) with VEC(3) while
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oring with VEC(4). Result is stored in VEC(4). */
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vpternlogd $0xf6, (VEC_SIZE * 2)(%rdx), %VMM(3), %VMM(4)
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/* Separate logic as we can only use testb for VEC_SIZE == 64.
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*/
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# if VEC_SIZE == 64
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testb %dil, %dil
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js L(8x_last_2x_vec)
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# else
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cmpl $(VEC_SIZE * 2), %edi
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jge L(8x_last_2x_vec)
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# endif
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VMOVU VEC_SIZE(%rsi, %rdx), %VMM(2)
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vpxorq VEC_SIZE(%rdx), %VMM(2), %VMM(2)
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VMOVU (%rsi, %rdx), %VMM(1)
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vpxorq (%rdx), %VMM(1), %VMM(1)
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vpternlogd $0xfe, %VMM(1), %VMM(2), %VMM(4)
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L(8x_last_1x_vec):
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L(8x_last_2x_vec):
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VPTEST %VMM(4), %VMM(4), %k1
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KMOV %k1, %VRAX
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TO_32BIT_P1 (rax)
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L(return_neq2):
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TO_32BIT_P2 (rax)
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ret
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.p2align 4,, 4
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L(last_2x_vec):
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VMOVU -(VEC_SIZE * 2)(%rsi, %rdx), %VMM(1)
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vpxorq -(VEC_SIZE * 2)(%rdi, %rdx), %VMM(1), %VMM(1)
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VMOVU -(VEC_SIZE * 1)(%rsi, %rdx), %VMM(2)
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vpternlogd $0xde, -(VEC_SIZE * 1)(%rdi, %rdx), %VMM(1), %VMM(2)
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VPTEST %VMM(2), %VMM(2), %k1
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KMOV %k1, %VRAX
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TO_32BIT (VRAX)
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ret
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/* evex256: 1 Bytes from next cache line. evex512: 15 Bytes from
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next cache line. */
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END (MEMCMPEQ)
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#endif
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