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70c97f8493
The tail of the copy loops are unable to train the falkor hardware prefetcher because they load from a different base compared to the hot loop. In this case avoid serializing the instructions by loading them into different registers. Also peel the last iteration of the loop into the tail (and have them use different registers) since it gives better performance for medium sizes. This results in performance improvements of between 3% and 20% over the current falkor implementation for sizes between 128 bytes and 1K on the memmove-walk benchmark, thus mostly covering the regressions seen against the generic memmove. * sysdeps/aarch64/multiarch/memmove_falkor.S (__memmove_falkor): Use multiple registers to move data in loop tail.
243 lines
5.8 KiB
ArmAsm
243 lines
5.8 KiB
ArmAsm
/* Copyright (C) 2017-2018 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library. If not, see
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<http://www.gnu.org/licenses/>. */
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#include <sysdep.h>
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/* Assumptions: ARMv8-a, AArch64, falkor, unaligned accesses. */
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#define dstin x0
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#define src x1
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#define count x2
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#define dstlen x3
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#define dst x3
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#define srcend x4
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#define dstend x5
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#define A_l x6
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#define A_lw w6
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#define A_h x7
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#define A_hw w7
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#define B_l x8
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#define B_lw w8
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#define B_h x9
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#define C_l x10
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#define C_h x11
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#define D_l x12
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#define D_h x13
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#define E_l src
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#define E_h count
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#define F_l srcend
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#define F_h dst
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#define tmp1 x14
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/* Alias with A_l and A_h to train the prefetcher. */
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#define Q_l x22
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#define Q_h x23
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/* RATIONALE:
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The copy has 4 distinct parts:
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* Small copies of 16 bytes and under
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* Medium sized copies of 17-96 bytes
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* Large copies where the source address is higher than the destination
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(forward copies)
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* Large copies where the destination address is higher than the source
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(copy backward, or move).
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We use only two registerpairs x6,x7 and x22,x23 for the copies and copy 32
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bytes at a time to correctly train the hardware prefetcher for better
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throughput. */
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ENTRY_ALIGN (__memmove_falkor, 6)
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sub tmp1, dstin, src
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add srcend, src, count
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add dstend, dstin, count
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cmp count, 96
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ccmp tmp1, count, 2, hi
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b.lo L(move_long)
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cmp count, 16
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b.ls L(copy16)
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cmp count, 96
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b.hi L(copy_long)
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/* Medium copies: 17..96 bytes. */
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sub tmp1, count, 1
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ldp A_l, A_h, [src]
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tbnz tmp1, 6, L(copy96)
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ldp D_l, D_h, [srcend, -16]
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tbz tmp1, 5, 1f
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ldp B_l, B_h, [src, 16]
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ldp C_l, C_h, [srcend, -32]
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stp B_l, B_h, [dstin, 16]
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stp C_l, C_h, [dstend, -32]
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1:
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stp A_l, A_h, [dstin]
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stp D_l, D_h, [dstend, -16]
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ret
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.p2align 4
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/* Small copies: 0..16 bytes. */
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L(copy16):
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cmp count, 8
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b.lo 1f
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ldr A_l, [src]
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ldr A_h, [srcend, -8]
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str A_l, [dstin]
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str A_h, [dstend, -8]
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ret
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.p2align 4
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1:
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/* 4-7 */
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tbz count, 2, 1f
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ldr A_lw, [src]
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ldr A_hw, [srcend, -4]
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str A_lw, [dstin]
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str A_hw, [dstend, -4]
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ret
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.p2align 4
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1:
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/* 2-3 */
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tbz count, 1, 1f
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ldrh A_lw, [src]
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ldrh A_hw, [srcend, -2]
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strh A_lw, [dstin]
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strh A_hw, [dstend, -2]
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ret
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.p2align 4
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1:
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/* 0-1 */
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tbz count, 0, 1f
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ldrb A_lw, [src]
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strb A_lw, [dstin]
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1: ret
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.p2align 4
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/* Copy 64..96 bytes. Copy 64 bytes from the start and
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32 bytes from the end. */
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L(copy96):
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ldp B_l, B_h, [src, 16]
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ldp C_l, C_h, [src, 32]
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ldp D_l, D_h, [src, 48]
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ldp E_l, E_h, [srcend, -32]
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ldp F_l, F_h, [srcend, -16]
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stp A_l, A_h, [dstin]
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stp B_l, B_h, [dstin, 16]
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stp C_l, C_h, [dstin, 32]
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stp D_l, D_h, [dstin, 48]
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stp E_l, E_h, [dstend, -32]
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stp F_l, F_h, [dstend, -16]
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ret
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/* Align SRC to 16 byte alignment so that we don't cross cache line
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boundaries on both loads and stores. There are at least 96 bytes
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to copy, so copy 16 bytes unaligned and then align. The loop
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copies 32 bytes per iteration and prefetches one iteration ahead. */
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.p2align 4
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L(copy_long):
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mov B_l, Q_l
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mov B_h, Q_h
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ldp A_l, A_h, [src]
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and tmp1, src, 15
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bic src, src, 15
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sub dst, dstin, tmp1
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add count, count, tmp1 /* Count is now 16 too large. */
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ldp Q_l, Q_h, [src, 16]!
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stp A_l, A_h, [dstin]
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ldp A_l, A_h, [src, 16]!
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subs count, count, 32 + 64 + 16 /* Test and readjust count. */
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b.ls L(last64)
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L(loop64):
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subs count, count, 32
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stp Q_l, Q_h, [dst, 16]
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ldp Q_l, Q_h, [src, 16]!
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stp A_l, A_h, [dst, 32]!
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ldp A_l, A_h, [src, 16]!
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b.hi L(loop64)
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/* Write the last full set of 64 bytes. The remainder is at most 64
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bytes and at least 33 bytes, so it is safe to always copy 64 bytes
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from the end. */
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L(last64):
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ldp C_l, C_h, [srcend, -64]
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stp Q_l, Q_h, [dst, 16]
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mov Q_l, B_l
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mov Q_h, B_h
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ldp B_l, B_h, [srcend, -48]
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stp A_l, A_h, [dst, 32]
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ldp A_l, A_h, [srcend, -32]
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ldp D_l, D_h, [srcend, -16]
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stp C_l, C_h, [dstend, -64]
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stp B_l, B_h, [dstend, -48]
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stp A_l, A_h, [dstend, -32]
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stp D_l, D_h, [dstend, -16]
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ret
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.p2align 4
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L(move_long):
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cbz tmp1, 3f
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mov B_l, Q_l
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mov B_h, Q_h
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/* Align SRCEND to 16 byte alignment so that we don't cross cache line
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boundaries on both loads and stores. There are at least 96 bytes
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to copy, so copy 16 bytes unaligned and then align. The loop
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copies 32 bytes per iteration and prefetches one iteration ahead. */
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ldp A_l, A_h, [srcend, -16]
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and tmp1, srcend, 15
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sub srcend, srcend, tmp1
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ldp Q_l, Q_h, [srcend, -16]!
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stp A_l, A_h, [dstend, -16]
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sub count, count, tmp1
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ldp A_l, A_h, [srcend, -16]!
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sub dstend, dstend, tmp1
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subs count, count, 32 + 64
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b.ls 2f
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1:
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subs count, count, 32
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stp Q_l, Q_h, [dstend, -16]
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ldp Q_l, Q_h, [srcend, -16]!
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stp A_l, A_h, [dstend, -32]!
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ldp A_l, A_h, [srcend, -16]!
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b.hi 1b
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/* Write the last full set of 64 bytes. The remainder is at most 64
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bytes and at least 33 bytes, so it is safe to always copy 64 bytes
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from the start. */
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2:
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ldp C_l, C_h, [src, 48]
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stp Q_l, Q_h, [dstend, -16]
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mov Q_l, B_l
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mov Q_h, B_h
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ldp B_l, B_h, [src, 32]
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stp A_l, A_h, [dstend, -32]
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ldp A_l, A_h, [src, 16]
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ldp D_l, D_h, [src]
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stp C_l, C_h, [dstin, 48]
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stp B_l, B_h, [dstin, 32]
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stp A_l, A_h, [dstin, 16]
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stp D_l, D_h, [dstin]
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3: ret
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END (__memmove_falkor)
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libc_hidden_builtin_def (__memmove_falkor)
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