glibc/sysdeps/aarch64/fpu/Versions
Joe Ramsay 0fed0b250f aarch64/fpu: Add vector variants of pow
Plus a small amount of moving includes around in order to be able to
remove duplicate definition of asuint64.

Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
2024-05-21 14:38:49 +01:00

139 lines
2.6 KiB
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libmvec {
GLIBC_2.38 {
_ZGVnN2v_cos;
_ZGVnN2v_exp;
_ZGVnN2v_log;
_ZGVnN2v_sin;
_ZGVnN4v_cosf;
_ZGVnN4v_expf;
_ZGVnN4v_logf;
_ZGVnN4v_sinf;
_ZGVsMxv_cos;
_ZGVsMxv_cosf;
_ZGVsMxv_exp;
_ZGVsMxv_expf;
_ZGVsMxv_log;
_ZGVsMxv_logf;
_ZGVsMxv_sin;
_ZGVsMxv_sinf;
}
GLIBC_2.39 {
_ZGVnN2v_cosf;
_ZGVnN2v_expf;
_ZGVnN2v_logf;
_ZGVnN2v_sinf;
_ZGVnN4v_acosf;
_ZGVnN2v_acosf;
_ZGVnN2v_acos;
_ZGVsMxv_acosf;
_ZGVsMxv_acos;
_ZGVnN4v_asinf;
_ZGVnN2v_asinf;
_ZGVnN2v_asin;
_ZGVsMxv_asinf;
_ZGVsMxv_asin;
_ZGVnN4v_atanf;
_ZGVnN2v_atanf;
_ZGVnN2v_atan;
_ZGVsMxv_atanf;
_ZGVsMxv_atan;
_ZGVnN4vv_atan2f;
_ZGVnN2vv_atan2f;
_ZGVnN2vv_atan2;
_ZGVsMxvv_atan2f;
_ZGVsMxvv_atan2;
_ZGVnN4v_exp10f;
_ZGVnN2v_exp10f;
_ZGVnN2v_exp10;
_ZGVsMxv_exp10f;
_ZGVsMxv_exp10;
_ZGVnN4v_exp2f;
_ZGVnN2v_exp2f;
_ZGVnN2v_exp2;
_ZGVsMxv_exp2f;
_ZGVsMxv_exp2;
_ZGVnN4v_expm1f;
_ZGVnN2v_expm1f;
_ZGVnN2v_expm1;
_ZGVsMxv_expm1f;
_ZGVsMxv_expm1;
_ZGVnN4v_log10f;
_ZGVnN2v_log10f;
_ZGVnN2v_log10;
_ZGVsMxv_log10f;
_ZGVsMxv_log10;
_ZGVnN4v_log1pf;
_ZGVnN2v_log1pf;
_ZGVnN2v_log1p;
_ZGVsMxv_log1pf;
_ZGVsMxv_log1p;
_ZGVnN4v_log2f;
_ZGVnN2v_log2f;
_ZGVnN2v_log2;
_ZGVsMxv_log2f;
_ZGVsMxv_log2;
_ZGVnN4v_tanf;
_ZGVnN2v_tanf;
_ZGVnN2v_tan;
_ZGVsMxv_tanf;
_ZGVsMxv_tan;
}
GLIBC_2.40 {
_ZGVnN2v_acosh;
_ZGVnN2v_acoshf;
_ZGVnN4v_acoshf;
_ZGVsMxv_acosh;
_ZGVsMxv_acoshf;
_ZGVnN2v_asinh;
_ZGVnN2v_asinhf;
_ZGVnN4v_asinhf;
_ZGVsMxv_asinh;
_ZGVsMxv_asinhf;
_ZGVnN2v_atanh;
_ZGVnN2v_atanhf;
_ZGVnN4v_atanhf;
_ZGVsMxv_atanh;
_ZGVsMxv_atanhf;
_ZGVnN2v_cbrt;
_ZGVnN2v_cbrtf;
_ZGVnN4v_cbrtf;
_ZGVsMxv_cbrt;
_ZGVsMxv_cbrtf;
_ZGVnN2v_cosh;
_ZGVnN2v_coshf;
_ZGVnN4v_coshf;
_ZGVsMxv_cosh;
_ZGVsMxv_coshf;
_ZGVnN2v_erf;
_ZGVnN2v_erff;
_ZGVnN4v_erff;
_ZGVsMxv_erf;
_ZGVsMxv_erff;
_ZGVnN2v_erfc;
_ZGVnN2v_erfcf;
_ZGVnN4v_erfcf;
_ZGVsMxv_erfc;
_ZGVsMxv_erfcf;
_ZGVnN4vv_hypotf;
_ZGVnN2vv_hypotf;
_ZGVnN2vv_hypot;
_ZGVsMxvv_hypotf;
_ZGVsMxvv_hypot;
_ZGVnN4vv_powf;
_ZGVnN2vv_powf;
_ZGVnN2vv_pow;
_ZGVsMxvv_powf;
_ZGVsMxvv_pow;
_ZGVnN2v_sinh;
_ZGVnN2v_sinhf;
_ZGVnN4v_sinhf;
_ZGVsMxv_sinh;
_ZGVsMxv_sinhf;
_ZGVnN2v_tanh;
_ZGVnN2v_tanhf;
_ZGVnN4v_tanhf;
_ZGVsMxv_tanh;
_ZGVsMxv_tanhf;
}
}