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90a6ca8b28
Previously many routines used * to load from vector types stored
in the data table. This is emitted as ldr, which byte-swaps the
entire vector register, and causes bugs for big-endian when not
all lanes contain the same value. When a vector is to be used
this way, it has been replaced with an array and the load with an
explicit ld1 intrinsic, which byte-swaps only within lanes.
As well, many routines previously used non-standard GCC syntax
for vector operations such as indexing into vectors types with []
and assembling vectors using {}. This syntax should not be mixed
with ACLE, as the former does not respect endianness whereas the
latter does. Such examples have been replaced with, for instance,
vcombine_* and vgetq_lane* intrinsics. Helpers which only use the
GCC syntax, such as the v_call helpers, do not need changing as
they do not use intrinsics.
Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
144 lines
5.0 KiB
C
144 lines
5.0 KiB
C
/* Single-precision vector (AdvSIMD) exp10 function.
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Copyright (C) 2023-2024 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<https://www.gnu.org/licenses/>. */
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#include "v_math.h"
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#include "poly_advsimd_f32.h"
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#define ScaleBound 192.0f
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static const struct data
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{
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float32x4_t poly[5];
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float log10_2_and_inv[4];
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float32x4_t shift;
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#if !WANT_SIMD_EXCEPT
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float32x4_t scale_thresh;
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#endif
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} data = {
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/* Coefficients generated using Remez algorithm with minimisation of relative
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error.
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rel error: 0x1.89dafa3p-24
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abs error: 0x1.167d55p-23 in [-log10(2)/2, log10(2)/2]
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maxerr: 1.85943 +0.5 ulp. */
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.poly = { V4 (0x1.26bb16p+1f), V4 (0x1.5350d2p+1f), V4 (0x1.04744ap+1f),
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V4 (0x1.2d8176p+0f), V4 (0x1.12b41ap-1f) },
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.shift = V4 (0x1.8p23f),
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/* Stores constants 1/log10(2), log10(2)_high, log10(2)_low, 0. */
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.log10_2_and_inv = { 0x1.a934fp+1, 0x1.344136p-2, -0x1.ec10cp-27, 0 },
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#if !WANT_SIMD_EXCEPT
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.scale_thresh = V4 (ScaleBound)
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#endif
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};
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#define ExponentBias v_u32 (0x3f800000)
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#if WANT_SIMD_EXCEPT
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# define SpecialBound 38.0f /* rint(log10(2^127)). */
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# define TinyBound v_u32 (0x20000000) /* asuint (0x1p-63). */
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# define BigBound v_u32 (0x42180000) /* asuint (SpecialBound). */
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# define Thres v_u32 (0x22180000) /* BigBound - TinyBound. */
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static float32x4_t VPCS_ATTR NOINLINE
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special_case (float32x4_t x, float32x4_t y, uint32x4_t cmp)
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{
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/* If fenv exceptions are to be triggered correctly, fall back to the scalar
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routine to special lanes. */
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return v_call_f32 (exp10f, x, y, cmp);
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}
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#else
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# define SpecialBound 126.0f /* rint (log2 (2^127 / (1 + sqrt (2)))). */
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# define SpecialOffset v_u32 (0x82000000)
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# define SpecialBias v_u32 (0x7f000000)
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static float32x4_t VPCS_ATTR NOINLINE
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special_case (float32x4_t poly, float32x4_t n, uint32x4_t e, uint32x4_t cmp1,
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float32x4_t scale, const struct data *d)
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{
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/* 2^n may overflow, break it up into s1*s2. */
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uint32x4_t b = vandq_u32 (vclezq_f32 (n), SpecialOffset);
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float32x4_t s1 = vreinterpretq_f32_u32 (vaddq_u32 (b, SpecialBias));
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float32x4_t s2 = vreinterpretq_f32_u32 (vsubq_u32 (e, b));
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uint32x4_t cmp2 = vcagtq_f32 (n, d->scale_thresh);
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float32x4_t r2 = vmulq_f32 (s1, s1);
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float32x4_t r1 = vmulq_f32 (vfmaq_f32 (s2, poly, s2), s1);
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/* Similar to r1 but avoids double rounding in the subnormal range. */
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float32x4_t r0 = vfmaq_f32 (scale, poly, scale);
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float32x4_t r = vbslq_f32 (cmp1, r1, r0);
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return vbslq_f32 (cmp2, r2, r);
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}
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#endif
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/* Fast vector implementation of single-precision exp10.
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Algorithm is accurate to 2.36 ULP.
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_ZGVnN4v_exp10f(0x1.be2b36p+1) got 0x1.7e79c4p+11
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want 0x1.7e79cp+11. */
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float32x4_t VPCS_ATTR NOINLINE V_NAME_F1 (exp10) (float32x4_t x)
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{
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const struct data *d = ptr_barrier (&data);
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#if WANT_SIMD_EXCEPT
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/* asuint(x) - TinyBound >= BigBound - TinyBound. */
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uint32x4_t cmp = vcgeq_u32 (
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vsubq_u32 (vreinterpretq_u32_f32 (vabsq_f32 (x)), TinyBound), Thres);
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float32x4_t xm = x;
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/* If any lanes are special, mask them with 1 and retain a copy of x to allow
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special case handler to fix special lanes later. This is only necessary if
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fenv exceptions are to be triggered correctly. */
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if (__glibc_unlikely (v_any_u32 (cmp)))
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x = v_zerofy_f32 (x, cmp);
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#endif
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/* exp10(x) = 2^n * 10^r = 2^n * (1 + poly (r)),
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with poly(r) in [1/sqrt(2), sqrt(2)] and
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x = r + n * log10 (2), with r in [-log10(2)/2, log10(2)/2]. */
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float32x4_t log10_2_and_inv = vld1q_f32 (d->log10_2_and_inv);
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float32x4_t z = vfmaq_laneq_f32 (d->shift, x, log10_2_and_inv, 0);
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float32x4_t n = vsubq_f32 (z, d->shift);
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float32x4_t r = vfmsq_laneq_f32 (x, n, log10_2_and_inv, 1);
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r = vfmsq_laneq_f32 (r, n, log10_2_and_inv, 2);
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uint32x4_t e = vshlq_n_u32 (vreinterpretq_u32_f32 (z), 23);
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float32x4_t scale = vreinterpretq_f32_u32 (vaddq_u32 (e, ExponentBias));
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#if !WANT_SIMD_EXCEPT
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uint32x4_t cmp = vcagtq_f32 (n, v_f32 (SpecialBound));
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#endif
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float32x4_t r2 = vmulq_f32 (r, r);
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float32x4_t poly
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= vfmaq_f32 (vmulq_f32 (r, d->poly[0]),
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v_pairwise_poly_3_f32 (r, r2, d->poly + 1), r2);
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if (__glibc_unlikely (v_any_u32 (cmp)))
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#if WANT_SIMD_EXCEPT
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return special_case (xm, vfmaq_f32 (scale, poly, scale), cmp);
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#else
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return special_case (poly, n, e, cmp, scale, d);
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#endif
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return vfmaq_f32 (scale, poly, scale);
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}
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libmvec_hidden_def (V_NAME_F1 (exp10))
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HALF_WIDTH_ALIAS_F1 (exp10)
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