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0435403c9d
from __x86_64_core_cache_size_half. (init_cacheinfo): Compute shared cache size for AMD processors with shared L3 correctly. * sysdeps/x86_64/memcpy.S: Adjust for __x86_64_data_cache_size_half name change. Patch in large parts by Evandro Menezes.
546 lines
14 KiB
C
546 lines
14 KiB
C
/* x86_64 cache info.
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Copyright (C) 2003, 2004, 2006, 2007 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, write to the Free
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Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
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02111-1307 USA.
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*/
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#include <assert.h>
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#include <stdbool.h>
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#include <stdlib.h>
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#include <unistd.h>
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static const struct intel_02_cache_info
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{
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unsigned int idx;
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int name;
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long int size;
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long int assoc;
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long int linesize;
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} intel_02_known [] =
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{
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{ 0x06, _SC_LEVEL1_ICACHE_SIZE, 8192, 4, 32 },
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{ 0x08, _SC_LEVEL1_ICACHE_SIZE, 16384, 4, 32 },
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{ 0x0a, _SC_LEVEL1_DCACHE_SIZE, 8192, 2, 32 },
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{ 0x0c, _SC_LEVEL1_DCACHE_SIZE, 16384, 4, 32 },
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{ 0x22, _SC_LEVEL3_CACHE_SIZE, 524288, 4, 64 },
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{ 0x23, _SC_LEVEL3_CACHE_SIZE, 1048576, 8, 64 },
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{ 0x25, _SC_LEVEL3_CACHE_SIZE, 2097152, 8, 64 },
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{ 0x29, _SC_LEVEL3_CACHE_SIZE, 4194304, 8, 64 },
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{ 0x2c, _SC_LEVEL1_DCACHE_SIZE, 32768, 8, 64 },
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{ 0x30, _SC_LEVEL1_ICACHE_SIZE, 32768, 8, 64 },
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{ 0x39, _SC_LEVEL2_CACHE_SIZE, 131072, 4, 64 },
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{ 0x3a, _SC_LEVEL2_CACHE_SIZE, 196608, 6, 64 },
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{ 0x3b, _SC_LEVEL2_CACHE_SIZE, 131072, 2, 64 },
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{ 0x3c, _SC_LEVEL2_CACHE_SIZE, 262144, 4, 64 },
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{ 0x3d, _SC_LEVEL2_CACHE_SIZE, 393216, 6, 64 },
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{ 0x3e, _SC_LEVEL2_CACHE_SIZE, 524288, 4, 64 },
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{ 0x41, _SC_LEVEL2_CACHE_SIZE, 131072, 4, 32 },
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{ 0x42, _SC_LEVEL2_CACHE_SIZE, 262144, 4, 32 },
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{ 0x43, _SC_LEVEL2_CACHE_SIZE, 524288, 4, 32 },
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{ 0x44, _SC_LEVEL2_CACHE_SIZE, 1048576, 4, 32 },
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{ 0x45, _SC_LEVEL2_CACHE_SIZE, 2097152, 4, 32 },
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{ 0x46, _SC_LEVEL3_CACHE_SIZE, 4194304, 4, 64 },
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{ 0x47, _SC_LEVEL3_CACHE_SIZE, 8388608, 8, 64 },
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{ 0x48, _SC_LEVEL2_CACHE_SIZE, 3145728, 12, 64 },
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{ 0x49, _SC_LEVEL2_CACHE_SIZE, 4194304, 16, 64 },
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{ 0x4a, _SC_LEVEL3_CACHE_SIZE, 6291456, 12, 64 },
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{ 0x4b, _SC_LEVEL3_CACHE_SIZE, 8388608, 16, 64 },
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{ 0x4c, _SC_LEVEL3_CACHE_SIZE, 12582912, 12, 64 },
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{ 0x4d, _SC_LEVEL3_CACHE_SIZE, 16777216, 16, 64 },
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{ 0x4e, _SC_LEVEL2_CACHE_SIZE, 6291456, 24, 64 },
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{ 0x60, _SC_LEVEL1_DCACHE_SIZE, 16384, 8, 64 },
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{ 0x66, _SC_LEVEL1_DCACHE_SIZE, 8192, 4, 64 },
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{ 0x67, _SC_LEVEL1_DCACHE_SIZE, 16384, 4, 64 },
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{ 0x68, _SC_LEVEL1_DCACHE_SIZE, 32768, 4, 64 },
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{ 0x78, _SC_LEVEL2_CACHE_SIZE, 1048576, 8, 64 },
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{ 0x79, _SC_LEVEL2_CACHE_SIZE, 131072, 8, 64 },
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{ 0x7a, _SC_LEVEL2_CACHE_SIZE, 262144, 8, 64 },
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{ 0x7b, _SC_LEVEL2_CACHE_SIZE, 524288, 8, 64 },
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{ 0x7c, _SC_LEVEL2_CACHE_SIZE, 1048576, 8, 64 },
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{ 0x7d, _SC_LEVEL2_CACHE_SIZE, 2097152, 8, 64 },
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{ 0x7f, _SC_LEVEL2_CACHE_SIZE, 524288, 2, 64 },
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{ 0x82, _SC_LEVEL2_CACHE_SIZE, 262144, 8, 32 },
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{ 0x83, _SC_LEVEL2_CACHE_SIZE, 524288, 8, 32 },
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{ 0x84, _SC_LEVEL2_CACHE_SIZE, 1048576, 8, 32 },
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{ 0x85, _SC_LEVEL2_CACHE_SIZE, 2097152, 8, 32 },
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{ 0x86, _SC_LEVEL2_CACHE_SIZE, 524288, 4, 64 },
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{ 0x87, _SC_LEVEL2_CACHE_SIZE, 1048576, 8, 64 },
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};
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#define nintel_02_known (sizeof (intel_02_known) / sizeof (intel_02_known [0]))
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static int
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intel_02_known_compare (const void *p1, const void *p2)
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{
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const struct intel_02_cache_info *i1;
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const struct intel_02_cache_info *i2;
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i1 = (const struct intel_02_cache_info *) p1;
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i2 = (const struct intel_02_cache_info *) p2;
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if (i1->idx == i2->idx)
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return 0;
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return i1->idx < i2->idx ? -1 : 1;
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}
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static long int
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__attribute__ ((noinline))
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intel_check_word (int name, unsigned int value, bool *has_level_2,
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bool *no_level_2_or_3)
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{
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if ((value & 0x80000000) != 0)
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/* The register value is reserved. */
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return 0;
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/* Fold the name. The _SC_ constants are always in the order SIZE,
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ASSOC, LINESIZE. */
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int folded_name = (_SC_LEVEL1_ICACHE_SIZE
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+ ((name - _SC_LEVEL1_ICACHE_SIZE) / 3) * 3);
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while (value != 0)
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{
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unsigned int byte = value & 0xff;
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if (byte == 0x40)
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{
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*no_level_2_or_3 = true;
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if (folded_name == _SC_LEVEL3_CACHE_SIZE)
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/* No need to look further. */
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break;
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}
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else
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{
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if (byte == 0x49 && folded_name == _SC_LEVEL3_CACHE_SIZE)
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{
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/* Intel reused this value. For family 15, model 6 it
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specifies the 3rd level cache. Otherwise the 2nd
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level cache. */
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unsigned int eax;
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unsigned int ebx;
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unsigned int ecx;
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unsigned int edx;
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asm volatile ("cpuid"
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: "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
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: "0" (1));
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unsigned int family = ((eax >> 20) & 0xff) + ((eax >> 8) & 0xf);
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unsigned int model = ((((eax >>16) & 0xf) << 4)
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+ ((eax >> 4) & 0xf));
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if (family == 15 && model == 6)
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{
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/* The level 3 cache is encoded for this model like
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the level 2 cache is for other models. Pretend
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the caller asked for the level 2 cache. */
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name = (_SC_LEVEL2_CACHE_SIZE
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+ (name - _SC_LEVEL3_CACHE_SIZE));
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folded_name = _SC_LEVEL3_CACHE_SIZE;
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}
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}
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struct intel_02_cache_info *found;
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struct intel_02_cache_info search;
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search.idx = byte;
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found = bsearch (&search, intel_02_known, nintel_02_known,
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sizeof (intel_02_known[0]), intel_02_known_compare);
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if (found != NULL)
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{
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if (found->name == folded_name)
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{
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unsigned int offset = name - folded_name;
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if (offset == 0)
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/* Cache size. */
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return found->size;
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if (offset == 1)
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return found->assoc;
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assert (offset == 2);
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return found->linesize;
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}
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if (found->name == _SC_LEVEL2_CACHE_SIZE)
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*has_level_2 = true;
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}
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}
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/* Next byte for the next round. */
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value >>= 8;
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}
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/* Nothing found. */
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return 0;
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}
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static long int __attribute__ ((noinline))
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handle_intel (int name, unsigned int maxidx)
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{
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assert (maxidx >= 2);
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/* OK, we can use the CPUID instruction to get all info about the
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caches. */
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unsigned int cnt = 0;
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unsigned int max = 1;
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long int result = 0;
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bool no_level_2_or_3 = false;
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bool has_level_2 = false;
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while (cnt++ < max)
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{
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unsigned int eax;
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unsigned int ebx;
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unsigned int ecx;
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unsigned int edx;
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asm volatile ("cpuid"
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: "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
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: "0" (2));
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/* The low byte of EAX in the first round contain the number of
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rounds we have to make. At least one, the one we are already
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doing. */
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if (cnt == 1)
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{
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max = eax & 0xff;
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eax &= 0xffffff00;
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}
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/* Process the individual registers' value. */
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result = intel_check_word (name, eax, &has_level_2, &no_level_2_or_3);
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if (result != 0)
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return result;
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result = intel_check_word (name, ebx, &has_level_2, &no_level_2_or_3);
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if (result != 0)
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return result;
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result = intel_check_word (name, ecx, &has_level_2, &no_level_2_or_3);
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if (result != 0)
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return result;
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result = intel_check_word (name, edx, &has_level_2, &no_level_2_or_3);
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if (result != 0)
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return result;
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}
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if (name >= _SC_LEVEL2_CACHE_SIZE && name <= _SC_LEVEL3_CACHE_LINESIZE
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&& no_level_2_or_3)
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return -1;
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return 0;
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}
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static long int __attribute__ ((noinline))
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handle_amd (int name)
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{
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unsigned int eax;
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unsigned int ebx;
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unsigned int ecx;
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unsigned int edx;
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asm volatile ("cpuid"
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: "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
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: "0" (0x80000000));
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/* No level 4 cache (yet). */
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if (name > _SC_LEVEL3_CACHE_LINESIZE)
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return 0;
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unsigned int fn = 0x80000005 + (name >= _SC_LEVEL2_CACHE_SIZE);
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if (eax < fn)
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return 0;
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asm volatile ("cpuid"
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: "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
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: "0" (fn));
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if (name < _SC_LEVEL1_DCACHE_SIZE)
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{
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name += _SC_LEVEL1_DCACHE_SIZE - _SC_LEVEL1_ICACHE_SIZE;
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ecx = edx;
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}
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switch (name)
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{
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case _SC_LEVEL1_DCACHE_SIZE:
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return (ecx >> 14) & 0x3fc00;
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case _SC_LEVEL1_DCACHE_ASSOC:
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ecx >>= 16;
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if ((ecx & 0xff) == 0xff)
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/* Fully associative. */
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return (ecx << 2) & 0x3fc00;
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return ecx & 0xff;
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case _SC_LEVEL1_DCACHE_LINESIZE:
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return ecx & 0xff;
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case _SC_LEVEL2_CACHE_SIZE:
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return (ecx & 0xf000) == 0 ? 0 : (ecx >> 6) & 0x3fffc00;
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case _SC_LEVEL2_CACHE_ASSOC:
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switch ((ecx >> 12) & 0xf)
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{
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case 0:
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case 1:
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case 2:
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case 4:
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return (ecx >> 12) & 0xf;
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case 6:
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return 8;
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case 8:
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return 16;
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case 10:
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return 32;
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case 11:
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return 48;
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case 12:
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return 64;
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case 13:
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return 96;
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case 14:
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return 128;
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case 15:
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return ((ecx >> 6) & 0x3fffc00) / (ecx & 0xff);
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default:
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return 0;
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}
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/* NOTREACHED */
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case _SC_LEVEL2_CACHE_LINESIZE:
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return (ecx & 0xf000) == 0 ? 0 : ecx & 0xff;
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case _SC_LEVEL3_CACHE_SIZE:
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return (edx & 0xf000) == 0 ? 0 : (edx & 0x3ffc0000) << 1;
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case _SC_LEVEL3_CACHE_ASSOC:
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switch ((edx >> 12) & 0xf)
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{
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case 0:
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case 1:
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case 2:
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case 4:
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return (edx >> 12) & 0xf;
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case 6:
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return 8;
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case 8:
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return 16;
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case 10:
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return 32;
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case 11:
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return 48;
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case 12:
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return 64;
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case 13:
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return 96;
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case 14:
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return 128;
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case 15:
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return ((edx & 0x3ffc0000) << 1) / (edx & 0xff);
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default:
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return 0;
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}
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/* NOTREACHED */
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case _SC_LEVEL3_CACHE_LINESIZE:
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return (edx & 0xf000) == 0 ? 0 : edx & 0xff;
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default:
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assert (! "cannot happen");
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}
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return -1;
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}
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/* Get the value of the system variable NAME. */
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long int
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attribute_hidden
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__cache_sysconf (int name)
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{
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/* Find out what brand of processor. */
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unsigned int eax;
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unsigned int ebx;
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unsigned int ecx;
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unsigned int edx;
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asm volatile ("cpuid"
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: "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
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: "0" (0));
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/* This spells out "GenuineIntel". */
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if (ebx == 0x756e6547 && ecx == 0x6c65746e && edx == 0x49656e69)
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return handle_intel (name, eax);
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/* This spells out "AuthenticAMD". */
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if (ebx == 0x68747541 && ecx == 0x444d4163 && edx == 0x69746e65)
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return handle_amd (name);
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// XXX Fill in more vendors.
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/* CPU not known, we have no information. */
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return 0;
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}
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/* Half the data cache size for use in memory and string routines, typically
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L1 size. */
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long int __x86_64_data_cache_size_half attribute_hidden = 32 * 1024 / 2;
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/* Shared cache size for use in memory and string routines, typically
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L2 or L3 size. */
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long int __x86_64_shared_cache_size_half attribute_hidden = 1024 * 1024 / 2;
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/* PREFETCHW support flag for use in memory and string routines. */
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int __x86_64_prefetchw attribute_hidden;
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static void
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__attribute__((constructor))
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init_cacheinfo (void)
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{
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/* Find out what brand of processor. */
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unsigned int eax;
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unsigned int ebx;
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unsigned int ecx;
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unsigned int edx;
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int max_cpuid;
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int max_cpuid_ex;
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long int data = -1;
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long int shared = -1;
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unsigned int level;
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unsigned int threads = 0;
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asm volatile ("cpuid"
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: "=a" (max_cpuid), "=b" (ebx), "=c" (ecx), "=d" (edx)
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: "0" (0));
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/* This spells out "GenuineIntel". */
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if (ebx == 0x756e6547 && ecx == 0x6c65746e && edx == 0x49656e69)
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{
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data = handle_intel (_SC_LEVEL1_DCACHE_SIZE, max_cpuid);
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/* Try L3 first. */
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level = 3;
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shared = handle_intel (_SC_LEVEL3_CACHE_SIZE, max_cpuid);
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if (shared <= 0)
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{
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/* Try L2 otherwise. */
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level = 2;
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shared = handle_intel (_SC_LEVEL2_CACHE_SIZE, max_cpuid);
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}
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/* Figure out the number of logical threads that share the
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highest cache level. */
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if (max_cpuid >= 4)
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{
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int i = 0;
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/* Query until desired cache level is enumerated. */
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do
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{
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asm volatile ("cpuid"
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: "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
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: "0" (4), "2" (i++));
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}
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while (((eax >> 5) & 0x7) != level);
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threads = ((eax >> 14) & 0x3ff) + 1;
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}
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else
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{
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/* Assume that all logical threads share the highest cache level. */
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asm volatile ("cpuid"
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: "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
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: "0" (1));
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threads = (ebx >> 16) & 0xff;
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}
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/* Cap usage of highest cache level to the number of supported
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threads. */
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if (shared > 0 && threads > 0)
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shared /= threads;
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}
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/* This spells out "AuthenticAMD". */
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else if (ebx == 0x68747541 && ecx == 0x444d4163 && edx == 0x69746e65)
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{
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data = handle_amd (_SC_LEVEL1_DCACHE_SIZE);
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long int core = handle_amd (_SC_LEVEL2_CACHE_SIZE);
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shared = handle_amd (_SC_LEVEL3_CACHE_SIZE);
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/* Get maximum extended function. */
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asm volatile ("cpuid"
|
|
: "=a" (max_cpuid_ex), "=b" (ebx), "=c" (ecx), "=d" (edx)
|
|
: "0" (0x80000000));
|
|
|
|
if (shared <= 0)
|
|
/* No shared L3 cache. All we have is the L2 cache. */
|
|
shared = core;
|
|
else
|
|
{
|
|
/* Figure out the number of logical threads that share L3. */
|
|
if (max_cpuid_ex >= 0x80000008)
|
|
{
|
|
/* Get width of APIC ID. */
|
|
asm volatile ("cpuid"
|
|
: "=a" (max_cpuid_ex), "=b" (ebx), "=c" (ecx),
|
|
"=d" (edx)
|
|
: "0" (0x80000008));
|
|
threads = 1 << ((ecx >> 12) & 0x0f);
|
|
}
|
|
|
|
if (threads == 0)
|
|
{
|
|
/* If APIC ID width is not available, use logical
|
|
processor count. */
|
|
asm volatile ("cpuid"
|
|
: "=a" (max_cpuid_ex), "=b" (ebx), "=c" (ecx),
|
|
"=d" (edx)
|
|
: "0" (0x00000001));
|
|
|
|
if ((edx & (1 << 28)) != 0)
|
|
threads = (ebx >> 16) & 0xff;
|
|
}
|
|
|
|
/* Cap usage of highest cache level to the number of
|
|
supported threads. */
|
|
if (threads > 0)
|
|
shared /= threads;
|
|
|
|
/* Account for exclusive L2 and L3 caches. */
|
|
shared += core;
|
|
}
|
|
|
|
if (max_cpuid_ex >= 0x80000001)
|
|
{
|
|
asm volatile ("cpuid"
|
|
: "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
|
|
: "0" (0x80000001));
|
|
/* PREFETCHW || 3DNow! */
|
|
if ((ecx & 0x100) || (edx & 0x80000000))
|
|
__x86_64_prefetchw = -1;
|
|
}
|
|
}
|
|
|
|
if (data > 0)
|
|
__x86_64_data_cache_size_half = data / 2;
|
|
|
|
if (shared > 0)
|
|
__x86_64_shared_cache_size_half = shared / 2;
|
|
}
|