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a2e5da2cf4
Add Intel Linear Address Masking (LAM) support to <sys/platform/x86.h>. HAS_CPU_FEATURE (LAM) can be used to detect if LAM is enabled in CPU. LAM modifies the checking that is applied to 64-bit linear addresses, allowing software to use of the untranslated address bits for metadata.
687 lines
16 KiB
Plaintext
687 lines
16 KiB
Plaintext
@node Platform, Contributors, Maintenance, Top
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@c %MENU% Describe all platform-specific facilities provided
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@appendix Platform-specific facilities
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@Theglibc{} can provide machine-specific functionality.
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@menu
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* PowerPC:: Facilities Specific to the PowerPC Architecture
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* RISC-V:: Facilities Specific to the RISC-V Architecture
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* X86:: Facilities Specific to the X86 Architecture
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@end menu
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@node PowerPC
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@appendixsec PowerPC-specific Facilities
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Facilities specific to PowerPC that are not specific to a particular
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operating system are declared in @file{sys/platform/ppc.h}.
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@deftypefun {uint64_t} __ppc_get_timebase (void)
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@safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}}
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Read the current value of the Time Base Register.
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The @dfn{Time Base Register} is a 64-bit register that stores a monotonically
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incremented value updated at a system-dependent frequency that may be
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different from the processor frequency. More information is available in
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@cite{Power ISA 2.06b - Book II - Section 5.2}.
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@code{__ppc_get_timebase} uses the processor's time base facility directly
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without requiring assistance from the operating system, so it is very
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efficient.
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@end deftypefun
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@deftypefun {uint64_t} __ppc_get_timebase_freq (void)
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@safety{@prelim{}@mtunsafe{@mtuinit{}}@asunsafe{@asucorrupt{:init}}@acunsafe{@acucorrupt{:init}}}
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@c __ppc_get_timebase_freq=__get_timebase_freq @mtuinit @acsfd
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@c __get_clockfreq @mtuinit @asucorrupt:init @acucorrupt:init @acsfd
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@c the initialization of the static timebase_freq is not exactly
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@c safe, because hp_timing_t cannot be atomically set up.
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@c syscall:get_tbfreq ok
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@c open dup @acsfd
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@c read dup ok
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@c memcpy dup ok
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@c memmem dup ok
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@c close dup @acsfd
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Read the current frequency at which the Time Base Register is updated.
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This frequency is not related to the processor clock or the bus clock.
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It is also possible that this frequency is not constant. More information is
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available in @cite{Power ISA 2.06b - Book II - Section 5.2}.
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@end deftypefun
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The following functions provide hints about the usage of resources that are
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shared with other processors. They can be used, for example, if a program
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waiting on a lock intends to divert the shared resources to be used by other
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processors. More information is available in @cite{Power ISA 2.06b - Book II -
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Section 3.2}.
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@deftypefun {void} __ppc_yield (void)
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@safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}}
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Provide a hint that performance will probably be improved if shared resources
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dedicated to the executing processor are released for use by other processors.
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@end deftypefun
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@deftypefun {void} __ppc_mdoio (void)
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@safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}}
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Provide a hint that performance will probably be improved if shared resources
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dedicated to the executing processor are released until all outstanding storage
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accesses to caching-inhibited storage have been completed.
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@end deftypefun
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@deftypefun {void} __ppc_mdoom (void)
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@safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}}
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Provide a hint that performance will probably be improved if shared resources
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dedicated to the executing processor are released until all outstanding storage
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accesses to cacheable storage for which the data is not in the cache have been
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completed.
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@end deftypefun
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@deftypefun {void} __ppc_set_ppr_med (void)
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@safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}}
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Set the Program Priority Register to medium value (default).
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The @dfn{Program Priority Register} (PPR) is a 64-bit register that controls
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the program's priority. By adjusting the PPR value the programmer may
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improve system throughput by causing the system resources to be used
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more efficiently, especially in contention situations.
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The three unprivileged states available are covered by the functions
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@code{__ppc_set_ppr_med} (medium -- default), @code{__ppc_set_ppc_low} (low)
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and @code{__ppc_set_ppc_med_low} (medium low). More information
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available in @cite{Power ISA 2.06b - Book II - Section 3.1}.
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@end deftypefun
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@deftypefun {void} __ppc_set_ppr_low (void)
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@safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}}
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Set the Program Priority Register to low value.
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@end deftypefun
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@deftypefun {void} __ppc_set_ppr_med_low (void)
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@safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}}
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Set the Program Priority Register to medium low value.
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@end deftypefun
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Power ISA 2.07 extends the priorities that can be set to the Program Priority
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Register (PPR). The following functions implement the new priority levels:
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very low and medium high.
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@deftypefun {void} __ppc_set_ppr_very_low (void)
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@safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}}
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Set the Program Priority Register to very low value.
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@end deftypefun
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@deftypefun {void} __ppc_set_ppr_med_high (void)
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@safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}}
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Set the Program Priority Register to medium high value. The medium high
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priority is privileged and may only be set during certain time intervals by
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problem-state programs. If the program priority is medium high when the time
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interval expires or if an attempt is made to set the priority to medium high
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when it is not allowed, the priority is set to medium.
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@end deftypefun
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@node RISC-V
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@appendixsec RISC-V-specific Facilities
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Cache management facilities specific to RISC-V systems that implement the Linux
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ABI are declared in @file{sys/cachectl.h}.
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@deftypefun {void} __riscv_flush_icache (void *@var{start}, void *@var{end}, unsigned long int @var{flags})
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@safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}}
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Enforce ordering between stores and instruction cache fetches. The range of
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addresses over which ordering is enforced is specified by @var{start} and
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@var{end}. The @var{flags} argument controls the extent of this ordering, with
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the default behavior (a @var{flags} value of 0) being to enforce the fence on
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all threads in the current process. Setting the
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@code{SYS_RISCV_FLUSH_ICACHE_LOCAL} bit allows users to indicate that enforcing
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ordering on only the current thread is necessary. All other flag bits are
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reserved.
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@end deftypefun
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@node X86
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@appendixsec X86-specific Facilities
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Facilities specific to X86 that are not specific to a particular
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operating system are declared in @file{sys/platform/x86.h}.
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@deftypefun {const struct cpu_features *} __x86_get_cpu_features (unsigned int @var{max})
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@safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}}
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Return a pointer to x86 CPU feature structure used by query macros for x86
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CPU features. If @var{max} exceeds @code{COMMON_CPUID_INDEX_MAX} which
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is the limit of the CPUID leaves supported by @Theglibc{}, the function
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returns @code{NULL}, indicating that the queried processor feature is
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unsupported by @Theglibc{} run-time.
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@end deftypefun
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@deftypefn Macro int HAS_CPU_FEATURE (@var{name})
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This macro returns a nonzero value (true) if the processor has the feature
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@var{name}.
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@end deftypefn
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@deftypefn Macro int CPU_FEATURE_USABLE (@var{name})
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This macro returns a nonzero value (true) if the processor has the feature
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@var{name} and the feature is supported by the operating system.
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@end deftypefn
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The supported processor features are:
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@itemize @bullet
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@item
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@code{ACPI} -- Thermal Monitor and Software Controlled Clock Facilities.
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@item
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@code{ADX} -- ADX instruction extensions.
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@item
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@code{APIC} -- APIC On-Chip.
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@item
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@code{AES} -- The AES instruction extensions.
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@item
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@code{AESKLE} -- AES Key Locker instructions are enabled by OS.
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@item
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@code{AMX_BF16} -- Tile computational operations on bfloat16 numbers.
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@item
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@code{AMX_INT8} -- Tile computational operations on 8-bit numbers.
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@item
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@code{AMX_TILE} -- Tile architecture.
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@item
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@code{ARCH_CAPABILITIES} -- IA32_ARCH_CAPABILITIES MSR.
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@item
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@code{AVX} -- The AVX instruction extensions.
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@item
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@code{AVX2} -- The AVX2 instruction extensions.
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@item
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@code{AVX_VNNI} -- The AVX-VNNI instruction extensions.
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@item
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@code{AVX512_4FMAPS} -- The AVX512_4FMAPS instruction extensions.
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@item
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@code{AVX512_4VNNIW} -- The AVX512_4VNNIW instruction extensions.
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@item
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@code{AVX512_BF16} -- The AVX512_BF16 instruction extensions.
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@item
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@code{AVX512_BITALG} -- The AVX512_BITALG instruction extensions.
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@item
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@code{AVX512_FP16} -- The AVX512_FP16 instruction extensions.
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@item
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@code{AVX512_IFMA} -- The AVX512_IFMA instruction extensions.
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@item
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@code{AVX512_VBMI} -- The AVX512_VBMI instruction extensions.
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@item
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@code{AVX512_VBMI2} -- The AVX512_VBMI2 instruction extensions.
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@item
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@code{AVX512_VNNI} -- The AVX512_VNNI instruction extensions.
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@item
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@code{AVX512_VP2INTERSECT} -- The AVX512_VP2INTERSECT instruction
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extensions.
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@item
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@code{AVX512_VPOPCNTDQ} -- The AVX512_VPOPCNTDQ instruction extensions.
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@item
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@code{AVX512BW} -- The AVX512BW instruction extensions.
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@item
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@code{AVX512CD} -- The AVX512CD instruction extensions.
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@item
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@code{AVX512ER} -- The AVX512ER instruction extensions.
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@item
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@code{AVX512DQ} -- The AVX512DQ instruction extensions.
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@item
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@code{AVX512F} -- The AVX512F instruction extensions.
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@item
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@code{AVX512PF} -- The AVX512PF instruction extensions.
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@item
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@code{AVX512VL} -- The AVX512VL instruction extensions.
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@item
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@code{BMI1} -- BMI1 instructions.
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@item
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@code{BMI2} -- BMI2 instructions.
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@item
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@code{CLDEMOTE} -- CLDEMOTE instruction.
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@item
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@code{CLFLUSHOPT} -- CLFLUSHOPT instruction.
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@item
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@code{CLFSH} -- CLFLUSH instruction.
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@item
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@code{CLWB} -- CLWB instruction.
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@item
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@code{CMOV} -- Conditional Move instructions.
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@item
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@code{CMPXCHG16B} -- CMPXCHG16B instruction.
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@item
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@code{CNXT_ID} -- L1 Context ID.
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@item
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@code{CORE_CAPABILITIES} -- IA32_CORE_CAPABILITIES MSR.
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@item
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@code{CX8} -- CMPXCHG8B instruction.
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@item
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@code{DCA} -- Data prefetch from a memory mapped device.
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@item
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@code{DE} -- Debugging Extensions.
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@item
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@code{DEPR_FPU_CS_DS} -- Deprecates FPU CS and FPU DS values.
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@item
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@code{DS} -- Debug Store.
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@item
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@code{DS_CPL} -- CPL Qualified Debug Store.
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@item
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@code{DTES64} -- 64-bit DS Area.
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@item
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@code{EIST} -- Enhanced Intel SpeedStep technology.
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@item
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@code{ENQCMD} -- Enqueue Stores instructions.
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@item
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@code{ERMS} -- Enhanced REP MOVSB/STOSB.
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@item
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@code{F16C} -- 16-bit floating-point conversion instructions.
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@item
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@code{FMA} -- FMA extensions using YMM state.
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@item
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@code{FMA4} -- FMA4 instruction extensions.
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@item
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@code{FPU} -- X87 Floating Point Unit On-Chip.
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@item
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@code{FSGSBASE} -- RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE instructions.
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@item
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@code{FSRCS} -- Fast Short REP CMP and SCA.
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@item
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@code{FSRM} -- Fast Short REP MOV.
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@item
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@code{FSRS} -- Fast Short REP STO.
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@item
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@code{FXSR} -- FXSAVE and FXRSTOR instructions.
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@item
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@code{FZLRM} -- Fast Zero-Length REP MOV.
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@item
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@code{GFNI} -- GFNI instruction extensions.
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@item
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@code{HLE} -- HLE instruction extensions.
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@item
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@code{HTT} -- Max APIC IDs reserved field is Valid.
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@item
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@code{HRESET} -- History reset.
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@item
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@code{HYBRID} -- Hybrid processor.
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@item
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@code{IBRS_IBPB} -- Indirect branch restricted speculation (IBRS) and
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the indirect branch predictor barrier (IBPB).
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@item
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@code{IBT} -- Intel Indirect Branch Tracking instruction extensions.
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@item
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@code{INVARIANT_TSC} -- Invariant TSC.
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@item
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@code{INVPCID} -- INVPCID instruction.
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@item
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@code{KL} -- AES Key Locker instructions.
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@item
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@code{LAM} -- Linear Address Masking.
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@item
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@code{L1D_FLUSH} -- IA32_FLUSH_CMD MSR.
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@item
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@code{LAHF64_SAHF64} -- LAHF/SAHF available in 64-bit mode.
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@item
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@code{LM} -- Long mode.
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@item
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@code{LWP} -- Lightweight profiling.
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@item
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@code{LZCNT} -- LZCNT instruction.
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@item
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@code{MCA} -- Machine Check Architecture.
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@item
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@code{MCE} -- Machine Check Exception.
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@item
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@code{MD_CLEAR} -- MD_CLEAR.
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@item
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@code{MMX} -- Intel MMX Technology.
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@item
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@code{MONITOR} -- MONITOR/MWAIT instructions.
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@item
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@code{MOVBE} -- MOVBE instruction.
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@item
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@code{MOVDIRI} -- MOVDIRI instruction.
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@item
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@code{MOVDIR64B} -- MOVDIR64B instruction.
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@item
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@code{MPX} -- Intel Memory Protection Extensions.
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@item
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@code{MSR} -- Model Specific Registers RDMSR and WRMSR instructions.
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@item
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@code{MTRR} -- Memory Type Range Registers.
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@item
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@code{NX} -- No-execute page protection.
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@item
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@code{OSPKE} -- OS has set CR4.PKE to enable protection keys.
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@item
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@code{OSXSAVE} -- The OS has set CR4.OSXSAVE[bit 18] to enable
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XSETBV/XGETBV instructions to access XCR0 and to support processor
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extended state management using XSAVE/XRSTOR.
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@item
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@code{PAE} -- Physical Address Extension.
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@item
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@code{PAGE1GB} -- 1-GByte page.
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@item
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@code{PAT} -- Page Attribute Table.
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@item
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@code{PBE} -- Pending Break Enable.
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@item
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@code{PCID} -- Process-context identifiers.
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@item
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@code{PCLMULQDQ} -- PCLMULQDQ instruction.
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@item
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@code{PCONFIG} -- PCONFIG instruction.
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@item
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@code{PDCM} -- Perfmon and Debug Capability.
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@item
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@code{PGE} -- Page Global Bit.
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@item
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@code{PKS} -- Protection keys for supervisor-mode pages.
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@item
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@code{PKU} -- Protection keys for user-mode pages.
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@item
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@code{POPCNT} -- POPCNT instruction.
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@item
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@code{PREFETCHW} -- PREFETCHW instruction.
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@item
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@code{PREFETCHWT1} -- PREFETCHWT1 instruction.
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@item
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@code{PSE} -- Page Size Extension.
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@item
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@code{PSE_36} -- 36-Bit Page Size Extension.
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@item
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@code{PSN} -- Processor Serial Number.
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@item
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@code{RDPID} -- RDPID instruction.
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@item
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@code{RDRAND} -- RDRAND instruction.
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@item
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@code{RDSEED} -- RDSEED instruction.
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@item
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@code{RDT_A} -- Intel Resource Director Technology (Intel RDT) Allocation
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capability.
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@item
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@code{RDT_M} -- Intel Resource Director Technology (Intel RDT) Monitoring
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capability.
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@item
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@code{RDTSCP} -- RDTSCP instruction.
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@item
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@code{RTM} -- RTM instruction extensions.
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@item
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@code{SDBG} -- IA32_DEBUG_INTERFACE MSR for silicon debug.
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@item
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@code{SEP} -- SYSENTER and SYSEXIT instructions.
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@item
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@code{SERIALIZE} -- SERIALIZE instruction.
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@item
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@code{SGX} -- Intel Software Guard Extensions.
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@item
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@code{SGX_LC} -- SGX Launch Configuration.
|
|
|
|
@item
|
|
@code{SHA} -- SHA instruction extensions.
|
|
|
|
@item
|
|
@code{SHSTK} -- Intel Shadow Stack instruction extensions.
|
|
|
|
@item
|
|
@code{SMAP} -- Supervisor-Mode Access Prevention.
|
|
|
|
@item
|
|
@code{SMEP} -- Supervisor-Mode Execution Prevention.
|
|
|
|
@item
|
|
@code{SMX} -- Safer Mode Extensions.
|
|
|
|
@item
|
|
@code{SS} -- Self Snoop.
|
|
|
|
@item
|
|
@code{SSBD} -- Speculative Store Bypass Disable (SSBD).
|
|
|
|
@item
|
|
@code{SSE} -- Streaming SIMD Extensions.
|
|
|
|
@item
|
|
@code{SSE2} -- Streaming SIMD Extensions 2.
|
|
|
|
@item
|
|
@code{SSE3} -- Streaming SIMD Extensions 3.
|
|
|
|
@item
|
|
@code{SSE4_1} -- Streaming SIMD Extensions 4.1.
|
|
|
|
@item
|
|
@code{SSE4_2} -- Streaming SIMD Extensions 4.2.
|
|
|
|
@item
|
|
@code{SSE4A} -- SSE4A instruction extensions.
|
|
|
|
@item
|
|
@code{SSSE3} -- Supplemental Streaming SIMD Extensions 3.
|
|
|
|
@item
|
|
@code{STIBP} -- Single thread indirect branch predictors (STIBP).
|
|
|
|
@item
|
|
@code{SVM} -- Secure Virtual Machine.
|
|
|
|
@item
|
|
@code{SYSCALL_SYSRET} -- SYSCALL/SYSRET instructions.
|
|
|
|
@item
|
|
@code{TBM} -- Trailing bit manipulation instructions.
|
|
|
|
@item
|
|
@code{TM} -- Thermal Monitor.
|
|
|
|
@item
|
|
@code{TM2} -- Thermal Monitor 2.
|
|
|
|
@item
|
|
@code{TRACE} -- Intel Processor Trace.
|
|
|
|
@item
|
|
@code{TSC} -- Time Stamp Counter. RDTSC instruction.
|
|
|
|
@item
|
|
@code{TSC_ADJUST} -- IA32_TSC_ADJUST MSR.
|
|
|
|
@item
|
|
@code{TSC_DEADLINE} -- Local APIC timer supports one-shot operation
|
|
using a TSC deadline value.
|
|
|
|
@item
|
|
@code{TSXLDTRK} -- TSXLDTRK instructions.
|
|
|
|
@item
|
|
@code{UINTR} -- User interrupts.
|
|
|
|
@item
|
|
@code{UMIP} -- User-mode instruction prevention.
|
|
|
|
@item
|
|
@code{VAES} -- VAES instruction extensions.
|
|
|
|
@item
|
|
@code{VME} -- Virtual 8086 Mode Enhancements.
|
|
|
|
@item
|
|
@code{VMX} -- Virtual Machine Extensions.
|
|
|
|
@item
|
|
@code{VPCLMULQDQ} -- VPCLMULQDQ instruction.
|
|
|
|
@item
|
|
@code{WAITPKG} -- WAITPKG instruction extensions.
|
|
|
|
@item
|
|
@code{WBNOINVD} -- WBINVD/WBNOINVD instructions.
|
|
|
|
@item
|
|
@code{WIDE_KL} -- AES wide Key Locker instructions.
|
|
|
|
@item
|
|
@code{X2APIC} -- x2APIC.
|
|
|
|
@item
|
|
@code{XFD} -- Extended Feature Disable (XFD).
|
|
|
|
@item
|
|
@code{XGETBV_ECX_1} -- XGETBV with ECX = 1.
|
|
|
|
@item
|
|
@code{XOP} -- XOP instruction extensions.
|
|
|
|
@item
|
|
@code{XSAVE} -- The XSAVE/XRSTOR processor extended states feature, the
|
|
XSETBV/XGETBV instructions, and XCR0.
|
|
|
|
@item
|
|
@code{XSAVEC} -- XSAVEC instruction.
|
|
|
|
@item
|
|
@code{XSAVEOPT} -- XSAVEOPT instruction.
|
|
|
|
@item
|
|
@code{XSAVES} -- XSAVES/XRSTORS instructions.
|
|
|
|
@item
|
|
@code{XTPRUPDCTRL} -- xTPR Update Control.
|
|
|
|
@end itemize
|
|
|
|
You could query if a processor supports @code{AVX} with:
|
|
|
|
@smallexample
|
|
#include <sys/platform/x86.h>
|
|
|
|
int
|
|
support_avx (void)
|
|
@{
|
|
return HAS_CPU_FEATURE (AVX);
|
|
@}
|
|
@end smallexample
|
|
|
|
and if @code{AVX} is usable with:
|
|
|
|
@smallexample
|
|
#include <sys/platform/x86.h>
|
|
|
|
int
|
|
usable_avx (void)
|
|
@{
|
|
return CPU_FEATURE_USABLE (AVX);
|
|
@}
|
|
@end smallexample
|