glibc/sysdeps/riscv/rv32/rvf/s_lrintf.c
Zong Li 941a55cf59 RISC-V: Add hard float support for 32-bit CPUs
This patch adds support for hardware floating-point support for the
RV32IF and RV32IFD platforms.

Reviewed-by: Maciej W. Rozycki <macro@wdc.com>
2020-08-27 08:17:42 -07:00

32 lines
1.0 KiB
C

/* lrintf(). 32-bit RISC-V (RV32) version.
Copyright (C) 2020 Free Software Foundation, Inc.
This file is part of the GNU C Library.
The GNU C Library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
The GNU C Library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with the GNU C Library. If not, see
<https://www.gnu.org/licenses/>. */
#include <math.h>
#include <libm-alias-float.h>
#include <stdint.h>
long int
__lrintf (float x)
{
int32_t res;
asm ("fcvt.w.s %0, %1" : "=r" (res) : "f" (x));
return res;
}
libm_alias_float (__lrint, lrint)