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ccc9035a67
The m68k bits/fenv.h is in sysdeps/m68k/fpu/, meaning that no-FPU ColdFire instead gets the generic (top-level) bits/fenv.h. That top-level bits/fenv.h defines no rounding mode constants. That no longer works for building glibc tests: some tests fail to build (at least with warnings) if no rounding mode macros are defined, so at least FE_TONEAREST must be defined in all cases (as various architectures without rounding mode support indeed do), while __FE_UNDEFINED must be defined in the case where not all the standard rounding modes are supported. On general principles of supporting multilib toolchains with a single set of headers shared between multilibs for a given architecture, it's also desirable for the same bits/fenv.h header to work for both FPU and no-FPU configurations. Thus, this patch moves the m68k bits/fenv.h to sysdeps/m68k/bits/fenv.h, and inserts appropriate conditionals to handle the no-FPU case. All the exception macros, and FE_NOMASK_ENV, are disabled in the no-FPU case; FE_ALL_EXCEPT is defined to 0 in that case. All rounding modes except FE_TONEAREST are disabled in that case, and __FE_UNDEFINED is defined accordingly. To avoid an unnecessary ABI change, fenv_t is defined in the no-FPU case to match the definition it would have got from the generic bits/fenv.h. This suffices to get a clean glibc and testsuite build for this configuration with build-many-glibcs.py (and keeps a clean build for the other m68k configurations); it has not been otherwise tested. * sysdeps/m68k/fpu/bits/fenv.h: Move to .... * sysdeps/m68k/bits/fenv.h: ... here. [!__HAVE_68881__ && !__HAVE_FPU__ && !__mcffpu__] (FE_INEXACT): Do not define. [!__HAVE_68881__ && !__HAVE_FPU__ && !__mcffpu__] (FE_DIVBYZERO): Likewise. [!__HAVE_68881__ && !__HAVE_FPU__ && !__mcffpu__] (FE_UNDERFLOW): Likewise. [!__HAVE_68881__ && !__HAVE_FPU__ && !__mcffpu__] (FE_OVERFLOW): Likewise. [!__HAVE_68881__ && !__HAVE_FPU__ && !__mcffpu__] (FE_INVALID): Likewise. [!__HAVE_68881__ && !__HAVE_FPU__ && !__mcffpu__] (FE_ALL_EXCEPT): Define to 0. [!__HAVE_68881__ && !__HAVE_FPU__ && !__mcffpu__] (__FE_UNDEFINED): New enum constant. [!__HAVE_68881__ && !__HAVE_FPU__ && !__mcffpu__] (FE_TOWARDZERO): Do not define. [!__HAVE_68881__ && !__HAVE_FPU__ && !__mcffpu__] (FE_DOWNWARD): Likewise. [!__HAVE_68881__ && !__HAVE_FPU__ && !__mcffpu__] (FE_UPWARD): Likewise. [!__HAVE_68881__ && !__HAVE_FPU__ && !__mcffpu__] (fenv_t): Define to match generic bits/fenv.h. [!__HAVE_68881__ && !__HAVE_FPU__ && !__mcffpu__] (FE_NOMASK_ENV): Do not define.
132 lines
3.3 KiB
C
132 lines
3.3 KiB
C
/* Copyright (C) 1997-2018 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library. If not, see
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<http://www.gnu.org/licenses/>. */
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#ifndef _FENV_H
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# error "Never use <bits/fenv.h> directly; include <fenv.h> instead."
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#endif
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#if defined __HAVE_68881__ || defined __HAVE_FPU__ || defined __mcffpu__
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/* Define bits representing the exception. We use the bit positions of
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the appropriate bits in the FPSR Accrued Exception Byte. */
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enum
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{
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FE_INEXACT =
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# define FE_INEXACT (1 << 3)
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FE_INEXACT,
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FE_DIVBYZERO =
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# define FE_DIVBYZERO (1 << 4)
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FE_DIVBYZERO,
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FE_UNDERFLOW =
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# define FE_UNDERFLOW (1 << 5)
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FE_UNDERFLOW,
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FE_OVERFLOW =
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# define FE_OVERFLOW (1 << 6)
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FE_OVERFLOW,
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FE_INVALID =
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# define FE_INVALID (1 << 7)
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FE_INVALID
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};
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# define FE_ALL_EXCEPT \
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(FE_INEXACT | FE_DIVBYZERO | FE_UNDERFLOW | FE_OVERFLOW | FE_INVALID)
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/* The m68k FPU supports all of the four defined rounding modes. We use
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the bit positions in the FPCR Mode Control Byte as the values for the
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appropriate macros. */
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enum
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{
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FE_TONEAREST =
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# define FE_TONEAREST 0
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FE_TONEAREST,
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FE_TOWARDZERO =
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# define FE_TOWARDZERO (1 << 4)
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FE_TOWARDZERO,
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FE_DOWNWARD =
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# define FE_DOWNWARD (2 << 4)
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FE_DOWNWARD,
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FE_UPWARD =
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# define FE_UPWARD (3 << 4)
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FE_UPWARD
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};
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#else
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/* In the soft-float case, only rounding to nearest is supported, with
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no exceptions. */
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# define FE_ALL_EXCEPT 0
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enum
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{
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__FE_UNDEFINED = -1,
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FE_TONEAREST =
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# define FE_TONEAREST 0
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FE_TONEAREST
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};
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#endif
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/* Type representing exception flags. */
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typedef unsigned int fexcept_t;
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#if defined __HAVE_68881__ || defined __HAVE_FPU__ || defined __mcffpu__
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/* Type representing floating-point environment. This structure
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corresponds to the layout of the block written by `fmovem'. */
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typedef struct
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{
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unsigned int __control_register;
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unsigned int __status_register;
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unsigned int __instruction_address;
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}
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fenv_t;
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#else
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/* Keep ABI compatibility with the type used in the generic
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bits/fenv.h, formerly used for no-FPU ColdFire. */
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typedef struct
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{
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fexcept_t __excepts;
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}
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fenv_t;
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#endif
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/* If the default argument is used we use this value. */
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#define FE_DFL_ENV ((const fenv_t *) -1)
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#if defined __USE_GNU && (defined __HAVE_68881__ \
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|| defined __HAVE_FPU__ \
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|| defined __mcffpu__)
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/* Floating-point environment where none of the exceptions are masked. */
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# define FE_NOMASK_ENV ((const fenv_t *) -2)
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#endif
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#if __GLIBC_USE (IEC_60559_BFP_EXT)
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/* Type representing floating-point control modes. */
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typedef unsigned int femode_t;
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/* Default floating-point control modes. */
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# define FE_DFL_MODE ((const femode_t *) -1L)
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#endif
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