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2002-06-05 Brian Youmans <3diff@gnu.org> * sysdeps/ia64/fpu/e_acos.S: Added text of Intel license. * sysdeps/ia64/fpu/e_acosf.S: Likewise. * sysdeps/ia64/fpu/e_acosl.S: Likewise. * sysdeps/ia64/fpu/e_asin.S: Likewise. * sysdeps/ia64/fpu/e_asinf.S: Likewise. * sysdeps/ia64/fpu/e_asinl.S: Likewise. * sysdeps/ia64/fpu/e_atan2.S: Likewise. * sysdeps/ia64/fpu/e_atan2f.S: Likewise. * sysdeps/ia64/fpu/e_cosh.S: Likewise. * sysdeps/ia64/fpu/e_coshf.S: Likewise. * sysdeps/ia64/fpu/e_coshl.S: Likewise. * sysdeps/ia64/fpu/e_exp.S: Likewise. * sysdeps/ia64/fpu/e_expf.S: Likewise. * sysdeps/ia64/fpu/e_fmod.S: Likewise. * sysdeps/ia64/fpu/e_fmodf.S: Likewise. * sysdeps/ia64/fpu/e_fmodl.S: Likewise. * sysdeps/ia64/fpu/e_hypot.S: Likewise. * sysdeps/ia64/fpu/e_hypotf.S: Likewise. * sysdeps/ia64/fpu/e_hypotl.S: Likewise. * sysdeps/ia64/fpu/e_log.S: Likewise. * sysdeps/ia64/fpu/e_logf.S: Likewise. * sysdeps/ia64/fpu/e_pow.S: Likewise. * sysdeps/ia64/fpu/e_powf.S: Likewise. * sysdeps/ia64/fpu/e_powl.S: Likewise. * sysdeps/ia64/fpu/e_remainder.S: Likewise. * sysdeps/ia64/fpu/e_remainderf.S: Likewise. * sysdeps/ia64/fpu/e_remainderl.S: Likewise. * sysdeps/ia64/fpu/e_scalb.S: Likewise. * sysdeps/ia64/fpu/e_scalbf.S: Likewise. * sysdeps/ia64/fpu/e_scalbl.S: Likewise. * sysdeps/ia64/fpu/e_sinh.S: Likewise. * sysdeps/ia64/fpu/e_sinhf.S: Likewise. * sysdeps/ia64/fpu/e_sinhl.S: Likewise. * sysdeps/ia64/fpu/e_sqrt.S: Likewise. * sysdeps/ia64/fpu/e_sqrtf.S: Likewise. * sysdeps/ia64/fpu/e_sqrtl.S: Likewise. * sysdeps/ia64/fpu/libm_atan2_req.S: Likewise. * sysdeps/ia64/fpu/libm_error.c: Likewise. * sysdeps/ia64/fpu/libm_frexp4.S: Likewise. * sysdeps/ia64/fpu/libm_frexp4f.S: Likewise. * sysdeps/ia64/fpu/s_frexpl.c: Likewise. * sysdeps/ia64/fpu/s_ilogb.S: Likewise. * sysdeps/ia64/fpu/s_ilogbf.S: Likewise. * sysdeps/ia64/fpu/s_ilogbl.S: Likewise. * sysdeps/ia64/fpu/s_ldexp.S: Likewise. * sysdeps/ia64/fpu/s_ldexpf.S: Likewise. * sysdeps/ia64/fpu/s_ldexpl.S: Likewise. * sysdeps/ia64/fpu/s_log1p.S: Likewise. * sysdeps/ia64/fpu/s_log1pf.S: Likewise. * sysdeps/ia64/fpu/s_log1pl.S: Likewise. * sysdeps/ia64/fpu/s_logb.S: Likewise. * sysdeps/ia64/fpu/s_logbf.S: Likewise. * sysdeps/ia64/fpu/s_logbl.S: Likewise. * sysdeps/ia64/fpu/s_modf.S: Likewise. * sysdeps/ia64/fpu/s_modff.S: Likewise. * sysdeps/ia64/fpu/s_modfl.S: Likewise. * sysdeps/ia64/fpu/s_nearbyint.S: Likewise. * sysdeps/ia64/fpu/s_nearbyintf.S: Likewise. * sysdeps/ia64/fpu/s_nearbyintl.S: Likewise. * sysdeps/ia64/fpu/s_rint.S: Likewise. * sysdeps/ia64/fpu/s_rintf.S: Likewise. * sysdeps/ia64/fpu/s_rintl.S: Likewise. * sysdeps/ia64/fpu/s_round.S: Likewise. * sysdeps/ia64/fpu/s_roundf.S: Likewise. * sysdeps/ia64/fpu/s_roundl.S: Likewise. * sysdeps/ia64/fpu/s_scalbn.S: Likewise. * sysdeps/ia64/fpu/s_scalbnf.S: Likewise. * sysdeps/ia64/fpu/s_scalbnl.S: Likewise. * sysdeps/ia64/fpu/s_significand.S: Likewise. * sysdeps/ia64/fpu/s_significandf.S: Likewise. * sysdeps/ia64/fpu/s_significandl.S: Likewise. * sysdeps/ia64/fpu/s_tan.S: Likewise. * sysdeps/ia64/fpu/s_tanf.S: Likewise. * sysdeps/ia64/fpu/s_tanl.S: Likewise. * sysdeps/ia64/fpu/s_trunc.S: Likewise. * sysdeps/ia64/fpu/s_truncf.S: Likewise. * sysdeps/ia64/fpu/s_truncl.S: Likewise. * sysdeps/ieee754/dbl-64/doasin.c: Changed copyright notice to reflect IBM donation of math library to FSF * sysdeps/ieee754/dbl-64/dosincos.c: Likewise. * sysdeps/ieee754/dbl-64/e_asin.c: Likewise. * sysdeps/ieee754/dbl-64/e_atan2.c: Likewise. * sysdeps/ieee754/dbl-64/e_exp.c: Likewise. * sysdeps/ieee754/dbl-64/e_log.c: Likewise. * sysdeps/ieee754/dbl-64/e_pow.c: Likewise. * sysdeps/ieee754/dbl-64/e_remainder.c: Likewise. * sysdeps/ieee754/dbl-64/e_sqrt.c: Likewise. * sysdeps/ieee754/dbl-64/halfulp.c: Likewise. * sysdeps/ieee754/dbl-64/mpa.c: Likewise. * sysdeps/ieee754/dbl-64/mpatan.c: Likewise. * sysdeps/ieee754/dbl-64/mpatan2.c: Likewise. * sysdeps/ieee754/dbl-64/mpexp.c: Likewise. * sysdeps/ieee754/dbl-64/mplog.c: Likewise. * sysdeps/ieee754/dbl-64/mpsqrt.c: Likewise. * sysdeps/ieee754/dbl-64/mptan.c: Likewise. * sysdeps/ieee754/dbl-64/s_atan.c: Likewise. * sysdeps/ieee754/dbl-64/s_sin.c: Likewise. * sysdeps/ieee754/dbl-64/s_tan.c: Likewise. * sysdeps/ieee754/dbl-64/sincos32.c: Likewise. * sysdeps/ieee754/dbl-64/slowexp.c: Likewise. * sysdeps/ieee754/dbl-64/slowpow.c: Likewise. * sysdeps/gnu/netinet/udp.h: Added BSD copying permission notice * sysdeps/vax/__longjmp.c: Likewise. * sysdeps/vax/setjmp.c: Likewise. * libio/filedoalloc.c: Fixed BSD copying permission notice to remove advertising clause * sysdeps/vax/htonl.s: Likewise. * sysdeps/vax/htons.s: Likewise. * libio/wfiledoalloc.c: Likewise. * stdlib/random.c: Likewise. * stdlib/random_r.c: Likewise. * sysdeps/mach/sys/reboot.h: Likewise. * inet/getnameinfo.c: Deleted advertising clause from Inner Net License * sysdeps/posix/getaddrinfo.c: Likewise. * sunrpc/des_impl.c: Updated license permission notice to Lesser GPL and corrected pointer to point to the correct license.
235 lines
6.1 KiB
ArmAsm
235 lines
6.1 KiB
ArmAsm
.file "nearbyintf.s"
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// Copyright (C) 2000, 2001, Intel Corporation
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// All rights reserved.
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//
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// Contributed 10/19/2000 by John Harrison, Cristina Iordache, Ted Kubaska,
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// Bob Norin, Tom Rowan, Shane Story, and Ping Tak Peter Tang of the
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// Computational Software Lab, Intel Corporation.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met:
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//
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// * Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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//
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// * The name of Intel Corporation may not be used to endorse or promote
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// products derived from this software without specific prior written
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// permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL INTEL OR ITS
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
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// OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT (INCLUDING
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// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Intel Corporation is the author of this code, and requests that all
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// problem reports or change requests be submitted to it directly at
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// http://developer.intel.com/opensource.
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//
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// History
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//==============================================================
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// 10/19/2000: Created
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// 2/08/01 Corrected behavior for all rounding modes.
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//==============================================================
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//
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// API
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//==============================================================
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// float nearbyintf(float x)
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#include "libm_support.h"
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//
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// general registers used:
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//
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nearbyint_GR_signexp = r14
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nearbyint_GR_exponent = r15
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nearbyint_GR_17ones = r16
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nearbyint_GR_10033 = r17
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nearbyint_GR_fpsr = r18
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nearbyint_GR_rcs0 = r19
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nearbyint_GR_rcs0_mask = r20
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// predicate registers used:
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// p6-11
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// floating-point registers used:
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NEARBYINT_NORM_f8 = f9
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NEARBYINT_FLOAT_INT_f8 = f10
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NEARBYINT_INT_f8 = f11
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// Overview of operation
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//==============================================================
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// float nearbyintf(float x)
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// Return an integer value (represented as a float) that is x rounded to integer in current
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// rounding mode
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// *******************************************************************************
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// Set denormal flag for denormal input and
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// and take denormal fault if necessary.
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// Is the input an integer value already?
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// double_extended
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// if the exponent is >= 1003e => 3F(true) = 63(decimal)
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// we have a significand of 64 bits 1.63-bits.
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// If we multiply by 2^63, we no longer have a fractional part
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// So input is an integer value already.
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// double
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// if the exponent is >= 10033 => 34(true) = 52(decimal)
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// 34 + 3ff = 433
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// we have a significand of 53 bits 1.52-bits. (implicit 1)
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// If we multiply by 2^52, we no longer have a fractional part
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// So input is an integer value already.
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// single
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// if the exponent is >= 10016 => 17(true) = 23(decimal)
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// we have a significand of 53 bits 1.52-bits. (implicit 1)
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// If we multiply by 2^52, we no longer have a fractional part
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// So input is an integer value already.
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// If x is NAN, ZERO, or INFINITY, then return
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// qnan snan inf norm unorm 0 -+
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// 1 1 1 0 0 1 11 0xe7
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.align 32
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.global nearbyintf#
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.section .text
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.proc nearbyintf#
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.align 32
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nearbyintf:
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{ .mfi
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mov nearbyint_GR_fpsr = ar40 // Read the fpsr--need to check rc.s0
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fcvt.fx.s1 NEARBYINT_INT_f8 = f8
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addl nearbyint_GR_10033 = 0x10016, r0
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}
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{ .mfi
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nop.m 999
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fnorm.s1 NEARBYINT_NORM_f8 = f8
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mov nearbyint_GR_17ones = 0x1FFFF
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;;
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}
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{ .mfi
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nop.m 999
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fclass.m.unc p6,p0 = f8, 0xe7
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mov nearbyint_GR_rcs0_mask = 0x0c00
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;;
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}
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{ .mfb
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nop.m 999
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(p6) fnorm.s f8 = f8
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(p6) br.ret.spnt b0 // Exit if x nan, inf, zero
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;;
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}
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{ .mfi
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nop.m 999
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fcvt.xf NEARBYINT_FLOAT_INT_f8 = NEARBYINT_INT_f8
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nop.i 999
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;;
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}
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{ .mfi
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getf.exp nearbyint_GR_signexp = NEARBYINT_NORM_f8
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fcmp.eq.s0 p8,p0 = f8,f0 // Dummy op to set denormal
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nop.i 999
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;;
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}
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{ .mii
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nop.m 999
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nop.i 999
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and nearbyint_GR_exponent = nearbyint_GR_signexp, nearbyint_GR_17ones
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;;
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}
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{ .mmi
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cmp.ge.unc p7,p6 = nearbyint_GR_exponent, nearbyint_GR_10033
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and nearbyint_GR_rcs0 = nearbyint_GR_rcs0_mask, nearbyint_GR_fpsr
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nop.i 999
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;;
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}
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// Check to see if s0 rounding mode is round to nearest. If not then set s2
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// rounding mode to that of s0 and repeat conversions.
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L(NEARBYINT_COMMON):
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{ .mfb
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cmp.ne p11,p0 = nearbyint_GR_rcs0, r0
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(p6) fclass.m.unc p9,p10 = NEARBYINT_FLOAT_INT_f8, 0x07 // Test for result=0
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(p11) br.cond.spnt L(NEARBYINT_NOT_ROUND_NEAREST) // Branch if not round to nearest
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;;
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}
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{ .mfi
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nop.m 999
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(p7) fnorm.s.s0 f8 = f8
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nop.i 999
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;;
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}
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// If result is zero, merge sign of input
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{ .mfi
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nop.m 999
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(p9) fmerge.s f8 = f8, NEARBYINT_FLOAT_INT_f8
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nop.i 999
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}
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{ .mfb
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nop.m 999
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(p10) fnorm.s f8 = NEARBYINT_FLOAT_INT_f8
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br.ret.sptk b0
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;;
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}
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L(NEARBYINT_NOT_ROUND_NEAREST):
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// Set rounding mode of s2 to that of s0
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{ .mfi
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mov nearbyint_GR_rcs0 = r0 // Clear so we don't come back here
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fsetc.s2 0x7f, 0x40
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nop.i 999
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;;
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}
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{ .mfi
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nop.m 999
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fcvt.fx.s2 NEARBYINT_INT_f8 = f8
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nop.i 999
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;;
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}
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{ .mfb
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nop.m 999
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fcvt.xf NEARBYINT_FLOAT_INT_f8 = NEARBYINT_INT_f8
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br.cond.sptk L(NEARBYINT_COMMON)
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;;
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}
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.endp nearbyintf
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ASM_SIZE_DIRECTIVE(nearbyintf)
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