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d5efd131d4
This is a simple copy of the last version of ia64 in the main tree. It does not work as-is, but serves as a basis for follow up changes to restore it to working order. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
351 lines
7.3 KiB
ArmAsm
351 lines
7.3 KiB
ArmAsm
/* From the Intel IA-64 Optimization Guide, choose the minimum latency
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alternative. */
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#include <sysdep.h>
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#undef ret
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#include <shlib-compat.h>
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#if SHLIB_COMPAT(libc, GLIBC_2_2, GLIBC_2_2_6)
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/* __divtf3
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Compute a 80-bit IEEE double-extended quotient.
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farg0 holds the dividend. farg1 holds the divisor. */
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ENTRY(___divtf3)
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cmp.eq p7, p0 = r0, r0
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frcpa.s0 f10, p6 = farg0, farg1
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;;
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(p6) cmp.ne p7, p0 = r0, r0
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.pred.rel.mutex p6, p7
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(p6) fnma.s1 f11 = farg1, f10, f1
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(p6) fma.s1 f12 = farg0, f10, f0
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;;
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(p6) fma.s1 f13 = f11, f11, f0
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(p6) fma.s1 f14 = f11, f11, f11
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;;
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(p6) fma.s1 f11 = f13, f13, f11
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(p6) fma.s1 f13 = f14, f10, f10
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;;
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(p6) fma.s1 f10 = f13, f11, f10
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(p6) fnma.s1 f11 = farg1, f12, farg0
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;;
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(p6) fma.s1 f11 = f11, f10, f12
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(p6) fnma.s1 f12 = farg1, f10, f1
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;;
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(p6) fma.s1 f10 = f12, f10, f10
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(p6) fnma.s1 f12 = farg1, f11, farg0
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;;
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(p6) fma.s0 fret0 = f12, f10, f11
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(p7) mov fret0 = f10
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br.ret.sptk rp
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END(___divtf3)
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.symver ___divtf3, __divtf3@GLIBC_2.2
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/* __divdf3
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Compute a 64-bit IEEE double quotient.
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farg0 holds the dividend. farg1 holds the divisor. */
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ENTRY(___divdf3)
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cmp.eq p7, p0 = r0, r0
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frcpa.s0 f10, p6 = farg0, farg1
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;;
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(p6) cmp.ne p7, p0 = r0, r0
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.pred.rel.mutex p6, p7
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(p6) fmpy.s1 f11 = farg0, f10
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(p6) fnma.s1 f12 = farg1, f10, f1
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;;
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(p6) fma.s1 f11 = f12, f11, f11
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(p6) fmpy.s1 f13 = f12, f12
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;;
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(p6) fma.s1 f10 = f12, f10, f10
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(p6) fma.s1 f11 = f13, f11, f11
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;;
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(p6) fmpy.s1 f12 = f13, f13
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(p6) fma.s1 f10 = f13, f10, f10
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;;
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(p6) fma.d.s1 f11 = f12, f11, f11
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(p6) fma.s1 f10 = f12, f10, f10
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;;
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(p6) fnma.d.s1 f8 = farg1, f11, farg0
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;;
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(p6) fma.d fret0 = f8, f10, f11
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(p7) mov fret0 = f10
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br.ret.sptk rp
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;;
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END(___divdf3)
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.symver ___divdf3, __divdf3@GLIBC_2.2
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/* __divsf3
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Compute a 32-bit IEEE float quotient.
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farg0 holds the dividend. farg1 holds the divisor. */
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ENTRY(___divsf3)
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cmp.eq p7, p0 = r0, r0
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frcpa.s0 f10, p6 = farg0, farg1
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;;
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(p6) cmp.ne p7, p0 = r0, r0
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.pred.rel.mutex p6, p7
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(p6) fmpy.s1 f8 = farg0, f10
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(p6) fnma.s1 f9 = farg1, f10, f1
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;;
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(p6) fma.s1 f8 = f9, f8, f8
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(p6) fmpy.s1 f9 = f9, f9
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;;
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(p6) fma.s1 f8 = f9, f8, f8
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(p6) fmpy.s1 f9 = f9, f9
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;;
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(p6) fma.d.s1 f10 = f9, f8, f8
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;;
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(p6) fnorm.s.s0 fret0 = f10
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(p7) mov fret0 = f10
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br.ret.sptk rp
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;;
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END(___divsf3)
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.symver ___divsf3, __divsf3@GLIBC_2.2
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/* __divdi3
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Compute a 64-bit integer quotient.
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in0 holds the dividend. in1 holds the divisor. */
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ENTRY(___divdi3)
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.regstk 2,0,0,0
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/* Transfer inputs to FP registers. */
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setf.sig f8 = in0
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setf.sig f9 = in1
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;;
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/* Convert the inputs to FP, so that they won't be treated as
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unsigned. */
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fcvt.xf f8 = f8
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fcvt.xf f9 = f9
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;;
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/* Compute the reciprocal approximation. */
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frcpa.s1 f10, p6 = f8, f9
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;;
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/* 3 Newton-Raphson iterations. */
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(p6) fnma.s1 f11 = f9, f10, f1
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(p6) fmpy.s1 f12 = f8, f10
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;;
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(p6) fmpy.s1 f13 = f11, f11
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(p6) fma.s1 f12 = f11, f12, f12
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;;
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(p6) fma.s1 f10 = f11, f10, f10
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(p6) fma.s1 f11 = f13, f12, f12
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;;
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(p6) fma.s1 f10 = f13, f10, f10
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(p6) fnma.s1 f12 = f9, f11, f8
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;;
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(p6) fma.s1 f10 = f12, f10, f11
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;;
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/* Round quotient to an integer. */
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fcvt.fx.trunc.s1 f10 = f10
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;;
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/* Transfer result to GP registers. */
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getf.sig ret0 = f10
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br.ret.sptk rp
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;;
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END(___divdi3)
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.symver ___divdi3, __divdi3@GLIBC_2.2
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/* __moddi3
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Compute a 64-bit integer modulus.
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in0 holds the dividend (a). in1 holds the divisor (b). */
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ENTRY(___moddi3)
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.regstk 2,0,0,0
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/* Transfer inputs to FP registers. */
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setf.sig f14 = in0
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setf.sig f9 = in1
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;;
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/* Convert the inputs to FP, so that they won't be treated as
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unsigned. */
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fcvt.xf f8 = f14
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fcvt.xf f9 = f9
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;;
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/* Compute the reciprocal approximation. */
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frcpa.s1 f10, p6 = f8, f9
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;;
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/* 3 Newton-Raphson iterations. */
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(p6) fmpy.s1 f12 = f8, f10
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(p6) fnma.s1 f11 = f9, f10, f1
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;;
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(p6) fma.s1 f12 = f11, f12, f12
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(p6) fmpy.s1 f13 = f11, f11
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;;
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(p6) fma.s1 f10 = f11, f10, f10
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(p6) fma.s1 f11 = f13, f12, f12
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;;
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sub in1 = r0, in1
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(p6) fma.s1 f10 = f13, f10, f10
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(p6) fnma.s1 f12 = f9, f11, f8
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;;
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setf.sig f9 = in1
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(p6) fma.s1 f10 = f12, f10, f11
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;;
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fcvt.fx.trunc.s1 f10 = f10
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;;
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/* r = q * (-b) + a */
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xma.l f10 = f10, f9, f14
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;;
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/* Transfer result to GP registers. */
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getf.sig ret0 = f10
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br.ret.sptk rp
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;;
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END(___moddi3)
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.symver ___moddi3, __moddi3@GLIBC_2.2
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/* __udivdi3
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Compute a 64-bit unsigned integer quotient.
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in0 holds the dividend. in1 holds the divisor. */
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ENTRY(___udivdi3)
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.regstk 2,0,0,0
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/* Transfer inputs to FP registers. */
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setf.sig f8 = in0
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setf.sig f9 = in1
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;;
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/* Convert the inputs to FP, to avoid FP software-assist faults. */
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fcvt.xuf.s1 f8 = f8
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fcvt.xuf.s1 f9 = f9
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;;
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/* Compute the reciprocal approximation. */
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frcpa.s1 f10, p6 = f8, f9
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;;
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/* 3 Newton-Raphson iterations. */
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(p6) fnma.s1 f11 = f9, f10, f1
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(p6) fmpy.s1 f12 = f8, f10
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;;
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(p6) fmpy.s1 f13 = f11, f11
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(p6) fma.s1 f12 = f11, f12, f12
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;;
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(p6) fma.s1 f10 = f11, f10, f10
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(p6) fma.s1 f11 = f13, f12, f12
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;;
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(p6) fma.s1 f10 = f13, f10, f10
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(p6) fnma.s1 f12 = f9, f11, f8
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;;
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(p6) fma.s1 f10 = f12, f10, f11
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;;
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/* Round quotient to an unsigned integer. */
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fcvt.fxu.trunc.s1 f10 = f10
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;;
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/* Transfer result to GP registers. */
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getf.sig ret0 = f10
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br.ret.sptk rp
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;;
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END(___udivdi3)
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.symver ___udivdi3, __udivdi3@GLIBC_2.2
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/* __umoddi3
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Compute a 64-bit unsigned integer modulus.
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in0 holds the dividend (a). in1 holds the divisor (b). */
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ENTRY(___umoddi3)
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.regstk 2,0,0,0
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/* Transfer inputs to FP registers. */
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setf.sig f14 = in0
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setf.sig f9 = in1
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;;
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/* Convert the inputs to FP, to avoid FP software assist faults. */
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fcvt.xuf.s1 f8 = f14
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fcvt.xuf.s1 f9 = f9
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;;
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/* Compute the reciprocal approximation. */
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frcpa.s1 f10, p6 = f8, f9
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;;
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/* 3 Newton-Raphson iterations. */
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(p6) fmpy.s1 f12 = f8, f10
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(p6) fnma.s1 f11 = f9, f10, f1
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;;
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(p6) fma.s1 f12 = f11, f12, f12
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(p6) fmpy.s1 f13 = f11, f11
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;;
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(p6) fma.s1 f10 = f11, f10, f10
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(p6) fma.s1 f11 = f13, f12, f12
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;;
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sub in1 = r0, in1
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(p6) fma.s1 f10 = f13, f10, f10
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(p6) fnma.s1 f12 = f9, f11, f8
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;;
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setf.sig f9 = in1
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(p6) fma.s1 f10 = f12, f10, f11
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;;
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/* Round quotient to an unsigned integer. */
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fcvt.fxu.trunc.s1 f10 = f10
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;;
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/* r = q * (-b) + a */
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xma.l f10 = f10, f9, f14
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;;
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/* Transfer result to GP registers. */
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getf.sig ret0 = f10
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br.ret.sptk rp
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;;
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END(___umoddi3)
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.symver ___umoddi3, __umoddi3@GLIBC_2.2
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/* __multi3
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Compute a 128-bit multiply of 128-bit multiplicands.
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in0/in1 holds one multiplicand (a), in2/in3 holds the other one (b). */
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ENTRY(___multi3)
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.regstk 4,0,0,0
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setf.sig f6 = in1
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movl r19 = 0xffffffff
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setf.sig f7 = in2
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;;
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and r14 = r19, in0
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;;
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setf.sig f10 = r14
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and r14 = r19, in2
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xmpy.l f9 = f6, f7
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;;
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setf.sig f6 = r14
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shr.u r14 = in0, 32
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;;
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setf.sig f7 = r14
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shr.u r14 = in2, 32
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;;
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setf.sig f8 = r14
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xmpy.l f11 = f10, f6
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xmpy.l f6 = f7, f6
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;;
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getf.sig r16 = f11
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xmpy.l f7 = f7, f8
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;;
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shr.u r14 = r16, 32
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and r16 = r19, r16
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getf.sig r17 = f6
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setf.sig f6 = in0
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;;
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setf.sig f11 = r14
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getf.sig r21 = f7
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setf.sig f7 = in3
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;;
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xma.l f11 = f10, f8, f11
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xma.l f6 = f6, f7, f9
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;;
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getf.sig r18 = f11
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;;
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add r18 = r18, r17
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;;
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and r15 = r19, r18
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cmp.ltu p7, p6 = r18, r17
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;;
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getf.sig r22 = f6
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(p7) adds r14 = 1, r19
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;;
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(p7) add r21 = r21, r14
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shr.u r14 = r18, 32
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shl r15 = r15, 32
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;;
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add r20 = r21, r14
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;;
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add ret0 = r15, r16
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add ret1 = r22, r20
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br.ret.sptk rp
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;;
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END(___multi3)
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.symver ___multi3, __multi3@GLIBC_2.2
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#endif
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