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540 lines
14 KiB
ArmAsm
540 lines
14 KiB
ArmAsm
/* Optimized 32-bit memset implementation for POWER6.
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Copyright (C) 1997-2016 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<http://www.gnu.org/licenses/>. */
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#include <sysdep.h>
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/* __ptr_t [r3] memset (__ptr_t s [r3], int c [r4], size_t n [r5]));
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Returns 's'.
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The memset is done in three sizes: byte (8 bits), word (32 bits),
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cache line (1024 bits). There is a special case for setting cache lines
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to 0, to take advantage of the dcbz instruction. */
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.machine power6
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EALIGN (memset, 7, 0)
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CALL_MCOUNT
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#define rTMP r0
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#define rRTN r3 /* Initial value of 1st argument. */
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#define rMEMP0 r3 /* Original value of 1st arg. */
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#define rCHR r4 /* Char to set in each byte. */
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#define rLEN r5 /* Length of region to set. */
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#define rMEMP r6 /* Address at which we are storing. */
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#define rALIGN r7 /* Number of bytes we are setting now (when aligning). */
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#define rMEMP2 r8
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#define rNEG64 r8 /* Constant -64 for clearing with dcbz. */
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#define rMEMP3 r9 /* Alt mem pointer. */
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L(_memset):
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/* Take care of case for size <= 4. */
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cmplwi cr1, rLEN, 4
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andi. rALIGN, rMEMP0, 3
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mr rMEMP, rMEMP0
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ble- cr1, L(small)
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/* Align to word boundary. */
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cmplwi cr5, rLEN, 31
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insrwi rCHR, rCHR, 8, 16 /* Replicate byte to halfword. */
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beq+ L(aligned)
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mtcrf 0x01, rMEMP0
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subfic rALIGN, rALIGN, 4
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add rMEMP, rMEMP, rALIGN
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sub rLEN, rLEN, rALIGN
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bf+ 31, L(g0)
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stb rCHR, 0(rMEMP0)
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bt 30, L(aligned)
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L(g0):
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sth rCHR, -2(rMEMP)
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.align 4
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/* Handle the case of size < 31. */
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L(aligned):
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mtcrf 0x01, rLEN
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insrwi rCHR, rCHR, 16, 0 /* Replicate halfword to word. */
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ble cr5, L(medium)
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/* Align to 32-byte boundary. */
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andi. rALIGN, rMEMP, 0x1C
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subfic rALIGN, rALIGN, 0x20
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beq L(caligned)
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mtcrf 0x01, rALIGN
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add rMEMP, rMEMP, rALIGN
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sub rLEN, rLEN, rALIGN
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cmplwi cr1, rALIGN, 0x10
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mr rMEMP2, rMEMP
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bf 28, L(a1)
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stw rCHR, -4(rMEMP2)
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stwu rCHR, -8(rMEMP2)
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nop
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L(a1): blt cr1, L(a2)
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stw rCHR, -4(rMEMP2)
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stw rCHR, -8(rMEMP2)
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stw rCHR, -12(rMEMP2)
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stwu rCHR, -16(rMEMP2)
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L(a2): bf 29, L(caligned)
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stw rCHR, -4(rMEMP2)
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.align 3
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/* Now aligned to a 32 byte boundary. */
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L(caligned):
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cmplwi cr1, rCHR, 0
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clrrwi. rALIGN, rLEN, 5
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mtcrf 0x01, rLEN
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beq cr1, L(zloopstart) /* Special case for clearing memory using dcbz. */
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L(nondcbz):
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beq L(medium) /* We may not actually get to do a full line. */
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nop
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/* Storing a non-zero "c" value. We are aligned at a sector (32-byte)
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boundary may not be at cache line (128-byte) boundary. */
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L(nzloopstart):
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/* memset in 32-byte chunks until we get to a cache line boundary.
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If rLEN is less than the distance to the next cache-line boundary use
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cacheAligned1 code to finish the tail. */
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cmplwi cr1,rLEN,128
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andi. rTMP,rMEMP,127
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blt cr1,L(cacheAligned1)
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addi rMEMP3,rMEMP,32
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beq L(nzCacheAligned)
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addi rLEN,rLEN,-32
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stw rCHR,0(rMEMP)
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stw rCHR,4(rMEMP)
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stw rCHR,8(rMEMP)
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stw rCHR,12(rMEMP)
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stw rCHR,16(rMEMP)
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stw rCHR,20(rMEMP)
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addi rMEMP,rMEMP,32
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andi. rTMP,rMEMP3,127
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stw rCHR,-8(rMEMP3)
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stw rCHR,-4(rMEMP3)
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beq L(nzCacheAligned)
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addi rLEN,rLEN,-32
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stw rCHR,0(rMEMP3)
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stw rCHR,4(rMEMP3)
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addi rMEMP,rMEMP,32
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stw rCHR,8(rMEMP3)
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stw rCHR,12(rMEMP3)
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andi. rTMP,rMEMP,127
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stw rCHR,16(rMEMP3)
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stw rCHR,20(rMEMP3)
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stw rCHR,24(rMEMP3)
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stw rCHR,28(rMEMP3)
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beq L(nzCacheAligned)
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addi rLEN,rLEN,-32
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/* At this point we can overrun the store queue (pipe reject) so it is
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time to slow things down. The store queue can merge two adjacent
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stores into a single L1/L2 op, but the L2 is clocked at 1/2 the CPU.
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So we add "group ending nops" to guarantee that we dispatch only two
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stores every other cycle. */
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ori r1,r1,0
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ori r1,r1,0
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stw rCHR,32(rMEMP3)
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stw rCHR,36(rMEMP3)
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addi rMEMP,rMEMP,32
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cmplwi cr1,rLEN,128
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ori r1,r1,0
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ori r1,r1,0
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stw rCHR,40(rMEMP3)
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stw rCHR,44(rMEMP3)
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ori r1,r1,0
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ori r1,r1,0
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stw rCHR,48(rMEMP3)
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stw rCHR,52(rMEMP3)
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ori r1,r1,0
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ori r1,r1,0
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stw rCHR,56(rMEMP3)
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stw rCHR,60(rMEMP3)
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blt cr1,L(cacheAligned1)
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b L(nzCacheAligned)
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/* Now we are aligned to the cache line and can use dcbtst. */
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.align 5
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L(nzCacheAligned):
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cmplwi cr1,rLEN,128
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cmplwi cr6,rLEN,256
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blt cr1,L(cacheAligned1)
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blt cr6,L(nzCacheAligned128)
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.align 4
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L(nzCacheAligned128):
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nop
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addi rMEMP3,rMEMP,64
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stw rCHR,0(rMEMP)
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stw rCHR,4(rMEMP)
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stw rCHR,8(rMEMP)
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stw rCHR,12(rMEMP)
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stw rCHR,16(rMEMP)
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stw rCHR,20(rMEMP)
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stw rCHR,24(rMEMP)
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stw rCHR,28(rMEMP)
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stw rCHR,32(rMEMP)
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stw rCHR,36(rMEMP)
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stw rCHR,40(rMEMP)
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stw rCHR,44(rMEMP)
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stw rCHR,48(rMEMP)
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stw rCHR,52(rMEMP)
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stw rCHR,56(rMEMP)
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stw rCHR,60(rMEMP)
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addi rMEMP,rMEMP3,64
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addi rLEN,rLEN,-128
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/* At this point we can overrun the store queue (pipe reject) so it is
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time to slow things down. The store queue can merge two adjacent
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stores into a single L1/L2 op, but the L2 is clocked at 1/2 the CPU.
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So we add "group ending nops" to guarantee that we dispatch only one
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store per cycle. */
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stw rCHR,0(rMEMP3)
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ori r1,r1,0
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stw rCHR,4(rMEMP3)
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ori r1,r1,0
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stw rCHR,8(rMEMP3)
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ori r1,r1,0
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stw rCHR,12(rMEMP3)
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ori r1,r1,0
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stw rCHR,16(rMEMP3)
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ori r1,r1,0
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stw rCHR,20(rMEMP3)
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ori r1,r1,0
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stw rCHR,24(rMEMP3)
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ori r1,r1,0
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stw rCHR,28(rMEMP3)
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ori r1,r1,0
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stw rCHR,32(rMEMP3)
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ori r1,r1,0
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stw rCHR,36(rMEMP3)
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ori r1,r1,0
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stw rCHR,40(rMEMP3)
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ori r1,r1,0
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stw rCHR,44(rMEMP3)
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ori r1,r1,0
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stw rCHR,48(rMEMP3)
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ori r1,r1,0
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stw rCHR,52(rMEMP3)
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ori r1,r1,0
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stw rCHR,56(rMEMP3)
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ori r1,r1,0
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stw rCHR,60(rMEMP3)
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blt cr6,L(cacheAligned1)
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#if IS_IN (libc)
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lfd 0,-128(rMEMP)
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#endif
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b L(nzCacheAligned256)
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.align 5
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L(nzCacheAligned256):
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cmplwi cr1,rLEN,256
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addi rMEMP3,rMEMP,64
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#if !IS_IN (libc)
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/* When we are not in libc we should use only GPRs to avoid the FPU lock
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interrupt. */
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stw rCHR,0(rMEMP)
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stw rCHR,4(rMEMP)
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stw rCHR,8(rMEMP)
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stw rCHR,12(rMEMP)
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stw rCHR,16(rMEMP)
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stw rCHR,20(rMEMP)
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stw rCHR,24(rMEMP)
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stw rCHR,28(rMEMP)
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stw rCHR,32(rMEMP)
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stw rCHR,36(rMEMP)
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stw rCHR,40(rMEMP)
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stw rCHR,44(rMEMP)
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stw rCHR,48(rMEMP)
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stw rCHR,52(rMEMP)
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stw rCHR,56(rMEMP)
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stw rCHR,60(rMEMP)
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addi rMEMP,rMEMP3,64
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addi rLEN,rLEN,-128
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stw rCHR,0(rMEMP3)
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stw rCHR,4(rMEMP3)
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stw rCHR,8(rMEMP3)
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stw rCHR,12(rMEMP3)
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stw rCHR,16(rMEMP3)
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stw rCHR,20(rMEMP3)
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stw rCHR,24(rMEMP3)
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stw rCHR,28(rMEMP3)
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stw rCHR,32(rMEMP3)
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stw rCHR,36(rMEMP3)
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stw rCHR,40(rMEMP3)
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stw rCHR,44(rMEMP3)
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stw rCHR,48(rMEMP3)
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stw rCHR,52(rMEMP3)
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stw rCHR,56(rMEMP3)
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stw rCHR,60(rMEMP3)
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#else
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/* We are in libc and this is a long memset so we can use FPRs and can afford
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occasional FPU locked interrupts. */
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stfd 0,0(rMEMP)
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stfd 0,8(rMEMP)
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stfd 0,16(rMEMP)
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stfd 0,24(rMEMP)
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stfd 0,32(rMEMP)
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stfd 0,40(rMEMP)
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stfd 0,48(rMEMP)
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stfd 0,56(rMEMP)
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addi rMEMP,rMEMP3,64
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addi rLEN,rLEN,-128
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stfd 0,0(rMEMP3)
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stfd 0,8(rMEMP3)
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stfd 0,16(rMEMP3)
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stfd 0,24(rMEMP3)
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stfd 0,32(rMEMP3)
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stfd 0,40(rMEMP3)
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stfd 0,48(rMEMP3)
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stfd 0,56(rMEMP3)
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#endif
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bge cr1,L(nzCacheAligned256)
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dcbtst 0,rMEMP
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b L(cacheAligned1)
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.align 4
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/* Storing a zero "c" value. We are aligned at a sector (32-byte)
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boundary but may not be at cache line (128-byte) boundary. If the
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remaining length spans a full cache line we can use the Data cache
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block zero instruction. */
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L(zloopstart):
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/* memset in 32-byte chunks until we get to a cache line boundary.
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If rLEN is less than the distance to the next cache-line boundary use
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cacheAligned1 code to finish the tail. */
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cmplwi cr1,rLEN,128
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beq L(medium)
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L(getCacheAligned):
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andi. rTMP,rMEMP,127
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blt cr1,L(cacheAligned1)
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addi rMEMP3,rMEMP,32
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beq L(cacheAligned)
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addi rLEN,rLEN,-32
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stw rCHR,0(rMEMP)
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stw rCHR,4(rMEMP)
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stw rCHR,8(rMEMP)
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stw rCHR,12(rMEMP)
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stw rCHR,16(rMEMP)
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stw rCHR,20(rMEMP)
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addi rMEMP,rMEMP,32
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andi. rTMP,rMEMP3,127
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stw rCHR,-8(rMEMP3)
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stw rCHR,-4(rMEMP3)
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L(getCacheAligned2):
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beq L(cacheAligned)
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addi rLEN,rLEN,-32
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addi rMEMP,rMEMP,32
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stw rCHR,0(rMEMP3)
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stw rCHR,4(rMEMP3)
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stw rCHR,8(rMEMP3)
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stw rCHR,12(rMEMP3)
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andi. rTMP,rMEMP,127
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nop
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stw rCHR,16(rMEMP3)
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stw rCHR,20(rMEMP3)
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stw rCHR,24(rMEMP3)
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stw rCHR,28(rMEMP3)
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L(getCacheAligned3):
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beq L(cacheAligned)
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/* At this point we can overrun the store queue (pipe reject) so it is
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time to slow things down. The store queue can merge two adjacent
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stores into a single L1/L2 op, but the L2 is clocked at 1/2 the CPU.
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So we add "group ending nops" to guarantee that we dispatch only two
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stores every other cycle. */
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addi rLEN,rLEN,-32
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ori r1,r1,0
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ori r1,r1,0
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stw rCHR,32(rMEMP3)
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stw rCHR,36(rMEMP3)
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addi rMEMP,rMEMP,32
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cmplwi cr1,rLEN,128
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ori r1,r1,0
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stw rCHR,40(rMEMP3)
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stw rCHR,44(rMEMP3)
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cmplwi cr6,rLEN,256
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li rMEMP2,128
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ori r1,r1,0
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stw rCHR,48(rMEMP3)
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stw rCHR,52(rMEMP3)
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ori r1,r1,0
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ori r1,r1,0
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stw rCHR,56(rMEMP3)
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stw rCHR,60(rMEMP3)
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blt cr1,L(cacheAligned1)
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blt cr6,L(cacheAligned128)
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b L(cacheAlignedx)
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/* Now we are aligned to the cache line and can use dcbz. */
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.align 4
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L(cacheAligned):
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cmplwi cr1,rLEN,128
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cmplwi cr6,rLEN,256
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blt cr1,L(cacheAligned1)
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li rMEMP2,128
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L(cacheAlignedx):
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cmplwi cr5,rLEN,640
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blt cr6,L(cacheAligned128)
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bgt cr5,L(cacheAligned512)
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cmplwi cr6,rLEN,512
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dcbz 0,rMEMP
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cmplwi cr1,rLEN,384
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dcbz rMEMP2,rMEMP
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addi rMEMP,rMEMP,256
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addi rLEN,rLEN,-256
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blt cr1,L(cacheAligned1)
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blt cr6,L(cacheAligned128)
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b L(cacheAligned256)
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.align 5
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/* A simple loop for the longer (>640 bytes) lengths. This form limits
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the branch miss-predicted to exactly 1 at loop exit.*/
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L(cacheAligned512):
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cmpli cr1,rLEN,128
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blt cr1,L(cacheAligned1)
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dcbz 0,rMEMP
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addi rLEN,rLEN,-128
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addi rMEMP,rMEMP,128
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b L(cacheAligned512)
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.align 5
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L(cacheAligned256):
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cmplwi cr6,rLEN,512
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dcbz 0,rMEMP
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cmplwi cr1,rLEN,384
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dcbz rMEMP2,rMEMP
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addi rMEMP,rMEMP,256
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addi rLEN,rLEN,-256
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bge cr6,L(cacheAligned256)
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blt cr1,L(cacheAligned1)
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.align 4
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L(cacheAligned128):
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dcbz 0,rMEMP
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addi rMEMP,rMEMP,128
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addi rLEN,rLEN,-128
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.align 4
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L(cacheAligned1):
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cmplwi cr1,rLEN,32
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blt cr1,L(handletail32)
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addi rMEMP3,rMEMP,32
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addi rLEN,rLEN,-32
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stw rCHR,0(rMEMP)
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stw rCHR,4(rMEMP)
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stw rCHR,8(rMEMP)
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stw rCHR,12(rMEMP)
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stw rCHR,16(rMEMP)
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stw rCHR,20(rMEMP)
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addi rMEMP,rMEMP,32
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cmplwi cr1,rLEN,32
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stw rCHR,-8(rMEMP3)
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stw rCHR,-4(rMEMP3)
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L(cacheAligned2):
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blt cr1,L(handletail32)
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addi rLEN,rLEN,-32
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stw rCHR,0(rMEMP3)
|
|
stw rCHR,4(rMEMP3)
|
|
stw rCHR,8(rMEMP3)
|
|
stw rCHR,12(rMEMP3)
|
|
addi rMEMP,rMEMP,32
|
|
cmplwi cr1,rLEN,32
|
|
stw rCHR,16(rMEMP3)
|
|
stw rCHR,20(rMEMP3)
|
|
stw rCHR,24(rMEMP3)
|
|
stw rCHR,28(rMEMP3)
|
|
nop
|
|
L(cacheAligned3):
|
|
blt cr1,L(handletail32)
|
|
/* At this point we can overrun the store queue (pipe reject) so it is
|
|
time to slow things down. The store queue can merge two adjacent
|
|
stores into a single L1/L2 op, but the L2 is clocked at 1/2 the CPU.
|
|
So we add "group ending nops" to guarantee that we dispatch only two
|
|
stores every other cycle. */
|
|
ori r1,r1,0
|
|
ori r1,r1,0
|
|
addi rMEMP,rMEMP,32
|
|
addi rLEN,rLEN,-32
|
|
ori r1,r1,0
|
|
ori r1,r1,0
|
|
stw rCHR,32(rMEMP3)
|
|
stw rCHR,36(rMEMP3)
|
|
ori r1,r1,0
|
|
ori r1,r1,0
|
|
stw rCHR,40(rMEMP3)
|
|
stw rCHR,44(rMEMP3)
|
|
ori r1,r1,0
|
|
ori r1,r1,0
|
|
stw rCHR,48(rMEMP3)
|
|
stw rCHR,52(rMEMP3)
|
|
ori r1,r1,0
|
|
ori r1,r1,0
|
|
stw rCHR,56(rMEMP3)
|
|
stw rCHR,60(rMEMP3)
|
|
|
|
/* We are here because the length or remainder (rLEN) is less than the
|
|
cache line/sector size and does not justify aggressive loop unrolling.
|
|
So set up the preconditions for L(medium) and go there. */
|
|
.align 3
|
|
L(handletail32):
|
|
cmplwi cr1,rLEN,0
|
|
beqlr cr1
|
|
b L(medium)
|
|
|
|
.align 4
|
|
L(small):
|
|
/* Memset of 4 bytes or less. */
|
|
cmplwi cr5, rLEN, 1
|
|
cmplwi cr1, rLEN, 3
|
|
bltlr cr5
|
|
stb rCHR, 0(rMEMP)
|
|
beqlr cr5
|
|
stb rCHR, 1(rMEMP)
|
|
bltlr cr1
|
|
stb rCHR, 2(rMEMP)
|
|
beqlr cr1
|
|
stb rCHR, 3(rMEMP)
|
|
blr
|
|
|
|
/* Memset of 0-31 bytes. */
|
|
.align 5
|
|
L(medium):
|
|
cmplwi cr1, rLEN, 16
|
|
L(medium_tail2):
|
|
add rMEMP, rMEMP, rLEN
|
|
L(medium_tail):
|
|
bt- 31, L(medium_31t)
|
|
bt- 30, L(medium_30t)
|
|
L(medium_30f):
|
|
bt 29, L(medium_29t)
|
|
L(medium_29f):
|
|
bge cr1, L(medium_27t)
|
|
bflr 28
|
|
stw rCHR, -4(rMEMP)
|
|
stw rCHR, -8(rMEMP)
|
|
blr
|
|
|
|
L(medium_31t):
|
|
stbu rCHR, -1(rMEMP)
|
|
bf- 30, L(medium_30f)
|
|
L(medium_30t):
|
|
sthu rCHR, -2(rMEMP)
|
|
bf- 29, L(medium_29f)
|
|
L(medium_29t):
|
|
stwu rCHR, -4(rMEMP)
|
|
blt cr1, L(medium_27f)
|
|
L(medium_27t):
|
|
stw rCHR, -4(rMEMP)
|
|
stw rCHR, -8(rMEMP)
|
|
stw rCHR, -12(rMEMP)
|
|
stwu rCHR, -16(rMEMP)
|
|
L(medium_27f):
|
|
bflr 28
|
|
L(medium_28t):
|
|
stw rCHR, -4(rMEMP)
|
|
stw rCHR, -8(rMEMP)
|
|
blr
|
|
END (memset)
|
|
libc_hidden_builtin_def (memset)
|