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sed -ri '
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s,(http|ftp)(://(.*\.)?)sources\.redhat\.com($|[^.]|\.[^a-z]),https\2sourceware.org\4,g
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! '(' -name configure \
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-print)
and then by running 'make dist-prepare' to regenerate files built
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# Omit irrelevant whitespace and comment-only changes,
# perhaps from a slightly-different Autoconf version.
git checkout -f \
sysdeps/csky/configure \
sysdeps/hppa/configure \
sysdeps/riscv/configure \
sysdeps/unix/sysv/linux/csky/configure
# Omit changes that caused a pre-commit check to fail like this:
# remote: *** error: sysdeps/powerpc/powerpc64/ppc-mcount.S: trailing lines
git checkout -f \
sysdeps/powerpc/powerpc64/ppc-mcount.S \
sysdeps/unix/sysv/linux/s390/s390-64/syscall.S
# Omit change that caused a pre-commit check to fail like this:
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git checkout -f sysdeps/sparc/sparc64/multiarch/memcpy-ultra3.S
133 lines
4.5 KiB
C
133 lines
4.5 KiB
C
/* FPU control word bits. Mips version.
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Copyright (C) 1996-2019 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library. If not, see
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<https://www.gnu.org/licenses/>. */
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#ifndef _FPU_CONTROL_H
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#define _FPU_CONTROL_H
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/* MIPS FPU floating point control register bits.
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*
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* 31-25 -> floating point conditions code bits 7-1. These bits are only
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* available in MIPS IV.
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* 24 -> flush denormalized results to zero instead of
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* causing unimplemented operation exception. This bit is only
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* available for MIPS III and newer.
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* 23 -> Condition bit
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* 22-21 -> reserved for architecture implementers
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* 20 -> reserved (read as 0, write with 0)
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* 19 -> IEEE 754-2008 non-arithmetic ABS.fmt and NEG.fmt enable
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* 18 -> IEEE 754-2008 recommended NaN encoding enable
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* 17 -> cause bit for unimplemented operation
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* 16 -> cause bit for invalid exception
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* 15 -> cause bit for division by zero exception
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* 14 -> cause bit for overflow exception
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* 13 -> cause bit for underflow exception
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* 12 -> cause bit for inexact exception
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* 11 -> enable exception for invalid exception
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* 10 -> enable exception for division by zero exception
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* 9 -> enable exception for overflow exception
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* 8 -> enable exception for underflow exception
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* 7 -> enable exception for inexact exception
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* 6 -> flag invalid exception
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* 5 -> flag division by zero exception
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* 4 -> flag overflow exception
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* 3 -> flag underflow exception
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* 2 -> flag inexact exception
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* 1-0 -> rounding control
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*
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*
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* Rounding Control:
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* 00 - rounding to nearest (RN)
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* 01 - rounding toward zero (RZ)
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* 10 - rounding (up) toward plus infinity (RP)
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* 11 - rounding (down)toward minus infinity (RM)
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*/
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#include <features.h>
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#ifdef __mips_soft_float
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#define _FPU_RESERVED 0xffffffff
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#define _FPU_DEFAULT 0x00000000
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typedef unsigned int fpu_control_t;
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#define _FPU_GETCW(cw) (cw) = 0
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#define _FPU_SETCW(cw) (void) (cw)
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extern fpu_control_t __fpu_control;
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#else /* __mips_soft_float */
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/* Masks for interrupts. */
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#define _FPU_MASK_V 0x0800 /* Invalid operation */
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#define _FPU_MASK_Z 0x0400 /* Division by zero */
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#define _FPU_MASK_O 0x0200 /* Overflow */
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#define _FPU_MASK_U 0x0100 /* Underflow */
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#define _FPU_MASK_I 0x0080 /* Inexact operation */
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/* Flush denormalized numbers to zero. */
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#define _FPU_FLUSH_TZ 0x1000000
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/* IEEE 754-2008 compliance control. */
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#define _FPU_ABS2008 0x80000
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#define _FPU_NAN2008 0x40000
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/* Rounding control. */
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#define _FPU_RC_NEAREST 0x0 /* RECOMMENDED */
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#define _FPU_RC_ZERO 0x1
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#define _FPU_RC_UP 0x2
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#define _FPU_RC_DOWN 0x3
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/* Mask for rounding control. */
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#define _FPU_RC_MASK 0x3
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#define _FPU_RESERVED 0xfe8c0000 /* Reserved bits in cw, incl ABS/NAN2008. */
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/* The fdlibm code requires strict IEEE double precision arithmetic,
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and no interrupts for exceptions, rounding to nearest. */
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#ifdef __mips_nan2008
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# define _FPU_DEFAULT 0x000C0000
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#else
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# define _FPU_DEFAULT 0x00000000
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#endif
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/* IEEE: same as above, but exceptions. */
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#ifdef __mips_nan2008
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# define _FPU_IEEE 0x000C0F80
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#else
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# define _FPU_IEEE 0x00000F80
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#endif
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/* Type of the control word. */
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typedef unsigned int fpu_control_t __attribute__ ((__mode__ (__SI__)));
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/* Macros for accessing the hardware control word. */
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extern fpu_control_t __mips_fpu_getcw (void) __THROW;
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extern void __mips_fpu_setcw (fpu_control_t) __THROW;
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#ifdef __mips16
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# define _FPU_GETCW(cw) do { (cw) = __mips_fpu_getcw (); } while (0)
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# define _FPU_SETCW(cw) __mips_fpu_setcw (cw)
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#else
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# define _FPU_GETCW(cw) __asm__ volatile ("cfc1 %0,$31" : "=r" (cw))
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# define _FPU_SETCW(cw) __asm__ volatile ("ctc1 %0,$31" : : "r" (cw))
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#endif
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/* Default control word set at startup. */
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extern fpu_control_t __fpu_control;
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#endif /* __mips_soft_float */
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#endif /* fpu_control.h */
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