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81cb7a0b2b
This semi-mechanical patch removes all uses and definitions of the
sfi_breg, sfi_pld, and sfi_sp macros from various ARM-specific
assembly files. These were only used by NaCl.
* sysdeps/arm/sysdep.h
(ARM_SFI_MACROS, sfi_breg, sfi_pld, sfi_sp): Delete definitions.
* sysdeps/arm/__longjmp.S, sysdeps/arm/add_n.S
* sysdeps/arm/addmul_1.S, sysdeps/arm/arm-mcount.S
* sysdeps/arm/armv6/rawmemchr.S, sysdeps/arm/armv6/strchr.S
* sysdeps/arm/armv6/strcpy.S, sysdeps/arm/armv6/strlen.S
* sysdeps/arm/armv6/strrchr.S, sysdeps/arm/armv6t2/memchr.S
* sysdeps/arm/armv6t2/strlen.S
* sysdeps/arm/armv7/multiarch/memcpy_impl.S
* sysdeps/arm/armv7/strcmp.S, sysdeps/arm/dl-tlsdesc.S
* sysdeps/arm/memcpy.S, sysdeps/arm/memmove.S
* sysdeps/arm/memset.S, sysdeps/arm/setjmp.S
* sysdeps/arm/strlen.S, sysdeps/arm/submul_1.S:
Remove all uses of sfi_breg, sfi_pld, and sfi_sp.
520 lines
12 KiB
ArmAsm
520 lines
12 KiB
ArmAsm
/* strcmp implementation for ARMv7-A, optimized for Cortex-A15.
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Copyright (C) 2012-2017 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library. If not, see
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<http://www.gnu.org/licenses/>. */
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#include <arm-features.h>
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#include <sysdep.h>
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/* Implementation of strcmp for ARMv7 when DSP instructions are
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available. Use ldrd to support wider loads, provided the data
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is sufficiently aligned. Use saturating arithmetic to optimize
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the compares. */
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/* Build Options:
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STRCMP_PRECHECK: Run a quick pre-check of the first byte in the
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string. If comparing completely random strings the pre-check will
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save time, since there is a very high probability of a mismatch in
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the first character: we save significant overhead if this is the
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common case. However, if strings are likely to be identical (e.g.
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because we're verifying a hit in a hash table), then this check
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is largely redundant. */
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#define STRCMP_PRECHECK 1
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.syntax unified
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#ifdef __ARM_BIG_ENDIAN
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# define S2LO lsl
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# define S2LOEQ lsleq
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# define S2HI lsr
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# define MSB 0x000000ff
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# define LSB 0xff000000
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# define BYTE0_OFFSET 24
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# define BYTE1_OFFSET 16
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# define BYTE2_OFFSET 8
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# define BYTE3_OFFSET 0
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#else /* not __ARM_BIG_ENDIAN */
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# define S2LO lsr
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# define S2LOEQ lsreq
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# define S2HI lsl
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# define BYTE0_OFFSET 0
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# define BYTE1_OFFSET 8
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# define BYTE2_OFFSET 16
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# define BYTE3_OFFSET 24
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# define MSB 0xff000000
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# define LSB 0x000000ff
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#endif /* not __ARM_BIG_ENDIAN */
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/* Parameters and result. */
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#define src1 r0
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#define src2 r1
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#define result r0 /* Overlaps src1. */
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/* Internal variables. */
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#define tmp1 r4
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#define tmp2 r5
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#define const_m1 r12
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/* Additional internal variables for 64-bit aligned data. */
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#define data1a r2
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#define data1b r3
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#define data2a r6
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#define data2b r7
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#define syndrome_a tmp1
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#define syndrome_b tmp2
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/* Additional internal variables for 32-bit aligned data. */
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#define data1 r2
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#define data2 r3
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#define syndrome tmp2
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#ifndef NO_THUMB
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/* This code is best on Thumb. */
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.thumb
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/* In Thumb code we can't use MVN with a register shift, but we do have ORN. */
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.macro prepare_mask mask_reg, nbits_reg
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S2HI \mask_reg, const_m1, \nbits_reg
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.endm
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.macro apply_mask data_reg, mask_reg
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orn \data_reg, \data_reg, \mask_reg
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.endm
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#else
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/* In ARM code we don't have ORN, but we can use MVN with a register shift. */
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.macro prepare_mask mask_reg, nbits_reg
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mvn \mask_reg, const_m1, S2HI \nbits_reg
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.endm
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.macro apply_mask data_reg, mask_reg
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orr \data_reg, \data_reg, \mask_reg
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.endm
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/* These clobber the condition codes, which the real Thumb cbz/cbnz
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instructions do not. But it doesn't matter for any of the uses here. */
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.macro cbz reg, label
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cmp \reg, #0
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beq \label
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.endm
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.macro cbnz reg, label
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cmp \reg, #0
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bne \label
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.endm
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#endif
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/* Macro to compute and return the result value for word-aligned
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cases. */
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.macro strcmp_epilogue_aligned synd d1 d2 restore_r6
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#ifdef __ARM_BIG_ENDIAN
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/* If data1 contains a zero byte, then syndrome will contain a 1 in
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bit 7 of that byte. Otherwise, the highest set bit in the
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syndrome will highlight the first different bit. It is therefore
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sufficient to extract the eight bits starting with the syndrome
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bit. */
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clz tmp1, \synd
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lsl r1, \d2, tmp1
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.if \restore_r6
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ldrd r6, r7, [sp, #8]
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.endif
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lsl \d1, \d1, tmp1
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lsr result, \d1, #24
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ldrd r4, r5, [sp], #16
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cfi_remember_state
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cfi_def_cfa_offset (0)
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cfi_restore (r4)
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cfi_restore (r5)
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cfi_restore (r6)
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cfi_restore (r7)
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sub result, result, r1, lsr #24
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bx lr
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#else
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/* To use the big-endian trick we'd have to reverse all three words.
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that's slower than this approach. */
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rev \synd, \synd
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clz tmp1, \synd
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bic tmp1, tmp1, #7
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lsr r1, \d2, tmp1
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.if \restore_r6
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ldrd r6, r7, [sp, #8]
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.endif
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lsr \d1, \d1, tmp1
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and result, \d1, #255
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and r1, r1, #255
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ldrd r4, r5, [sp], #16
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cfi_remember_state
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cfi_def_cfa_offset (0)
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cfi_restore (r4)
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cfi_restore (r5)
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cfi_restore (r6)
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cfi_restore (r7)
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sub result, result, r1
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bx lr
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#endif
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.endm
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.text
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.p2align 5
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.Lstrcmp_start_addr:
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#if STRCMP_PRECHECK == 1
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.Lfastpath_exit:
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sub r0, r2, r3
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bx lr
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nop
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#endif
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ENTRY (strcmp)
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#if STRCMP_PRECHECK == 1
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ldrb r2, [src1]
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ldrb r3, [src2]
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cmp r2, #1
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it cs
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cmpcs r2, r3
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bne .Lfastpath_exit
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#endif
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strd r4, r5, [sp, #-16]!
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cfi_def_cfa_offset (16)
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cfi_offset (r4, -16)
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cfi_offset (r5, -12)
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orr tmp1, src1, src2
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strd r6, r7, [sp, #8]
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cfi_offset (r6, -8)
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cfi_offset (r7, -4)
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mvn const_m1, #0
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lsl r2, tmp1, #29
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cbz r2, .Lloop_aligned8
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.Lnot_aligned:
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eor tmp1, src1, src2
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tst tmp1, #7
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bne .Lmisaligned8
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/* Deal with mutual misalignment by aligning downwards and then
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masking off the unwanted loaded data to prevent a difference. */
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and tmp1, src1, #7
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bic src1, src1, #7
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and tmp2, tmp1, #3
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bic src2, src2, #7
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lsl tmp2, tmp2, #3 /* Bytes -> bits. */
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ldrd data1a, data1b, [src1], #16
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tst tmp1, #4
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ldrd data2a, data2b, [src2], #16
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prepare_mask tmp1, tmp2
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apply_mask data1a, tmp1
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apply_mask data2a, tmp1
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beq .Lstart_realigned8
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apply_mask data1b, tmp1
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mov data1a, const_m1
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apply_mask data2b, tmp1
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mov data2a, const_m1
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b .Lstart_realigned8
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/* Unwind the inner loop by a factor of 2, giving 16 bytes per
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pass. */
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.p2align 5,,12 /* Don't start in the tail bytes of a cache line. */
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.p2align 2 /* Always word aligned. */
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.Lloop_aligned8:
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ldrd data1a, data1b, [src1], #16
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ldrd data2a, data2b, [src2], #16
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.Lstart_realigned8:
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uadd8 syndrome_b, data1a, const_m1 /* Only want GE bits, */
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eor syndrome_a, data1a, data2a
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sel syndrome_a, syndrome_a, const_m1
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cbnz syndrome_a, .Ldiff_in_a
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uadd8 syndrome_b, data1b, const_m1 /* Only want GE bits. */
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eor syndrome_b, data1b, data2b
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sel syndrome_b, syndrome_b, const_m1
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cbnz syndrome_b, .Ldiff_in_b
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ldrd data1a, data1b, [src1, #-8]
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ldrd data2a, data2b, [src2, #-8]
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uadd8 syndrome_b, data1a, const_m1 /* Only want GE bits, */
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eor syndrome_a, data1a, data2a
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sel syndrome_a, syndrome_a, const_m1
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uadd8 syndrome_b, data1b, const_m1 /* Only want GE bits. */
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eor syndrome_b, data1b, data2b
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sel syndrome_b, syndrome_b, const_m1
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/* Can't use CBZ for backwards branch. */
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orrs syndrome_b, syndrome_b, syndrome_a /* Only need if s_a == 0 */
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beq .Lloop_aligned8
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.Ldiff_found:
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cbnz syndrome_a, .Ldiff_in_a
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.Ldiff_in_b:
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strcmp_epilogue_aligned syndrome_b, data1b, data2b 1
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.Ldiff_in_a:
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cfi_restore_state
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strcmp_epilogue_aligned syndrome_a, data1a, data2a 1
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cfi_restore_state
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.Lmisaligned8:
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tst tmp1, #3
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bne .Lmisaligned4
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ands tmp1, src1, #3
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bne .Lmutual_align4
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/* Unrolled by a factor of 2, to reduce the number of post-increment
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operations. */
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.Lloop_aligned4:
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ldr data1, [src1], #8
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ldr data2, [src2], #8
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.Lstart_realigned4:
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uadd8 syndrome, data1, const_m1 /* Only need GE bits. */
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eor syndrome, data1, data2
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sel syndrome, syndrome, const_m1
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cbnz syndrome, .Laligned4_done
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ldr data1, [src1, #-4]
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ldr data2, [src2, #-4]
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uadd8 syndrome, data1, const_m1
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eor syndrome, data1, data2
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sel syndrome, syndrome, const_m1
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cmp syndrome, #0
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beq .Lloop_aligned4
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.Laligned4_done:
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strcmp_epilogue_aligned syndrome, data1, data2, 0
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.Lmutual_align4:
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cfi_restore_state
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/* Deal with mutual misalignment by aligning downwards and then
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masking off the unwanted loaded data to prevent a difference. */
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lsl tmp1, tmp1, #3 /* Bytes -> bits. */
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bic src1, src1, #3
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ldr data1, [src1], #8
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bic src2, src2, #3
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ldr data2, [src2], #8
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prepare_mask tmp1, tmp1
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apply_mask data1, tmp1
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apply_mask data2, tmp1
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b .Lstart_realigned4
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.Lmisaligned4:
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ands tmp1, src1, #3
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beq .Lsrc1_aligned
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sub src2, src2, tmp1
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bic src1, src1, #3
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lsls tmp1, tmp1, #31
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ldr data1, [src1], #4
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beq .Laligned_m2
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bcs .Laligned_m1
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#if STRCMP_PRECHECK == 0
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ldrb data2, [src2, #1]
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uxtb tmp1, data1, ror #BYTE1_OFFSET
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subs tmp1, tmp1, data2
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bne .Lmisaligned_exit
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cbz data2, .Lmisaligned_exit
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.Laligned_m2:
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ldrb data2, [src2, #2]
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uxtb tmp1, data1, ror #BYTE2_OFFSET
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subs tmp1, tmp1, data2
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bne .Lmisaligned_exit
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cbz data2, .Lmisaligned_exit
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.Laligned_m1:
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ldrb data2, [src2, #3]
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uxtb tmp1, data1, ror #BYTE3_OFFSET
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subs tmp1, tmp1, data2
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bne .Lmisaligned_exit
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add src2, src2, #4
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cbnz data2, .Lsrc1_aligned
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#else /* STRCMP_PRECHECK */
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/* If we've done the pre-check, then we don't need to check the
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first byte again here. */
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ldrb data2, [src2, #2]
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uxtb tmp1, data1, ror #BYTE2_OFFSET
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subs tmp1, tmp1, data2
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bne .Lmisaligned_exit
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cbz data2, .Lmisaligned_exit
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.Laligned_m2:
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ldrb data2, [src2, #3]
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uxtb tmp1, data1, ror #BYTE3_OFFSET
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subs tmp1, tmp1, data2
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bne .Lmisaligned_exit
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cbnz data2, .Laligned_m1
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#endif
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.Lmisaligned_exit:
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mov result, tmp1
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ldr r4, [sp], #16
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cfi_remember_state
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cfi_def_cfa_offset (0)
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cfi_restore (r4)
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cfi_restore (r5)
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cfi_restore (r6)
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cfi_restore (r7)
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bx lr
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#if STRCMP_PRECHECK == 1
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.Laligned_m1:
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add src2, src2, #4
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#endif
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.Lsrc1_aligned:
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cfi_restore_state
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/* src1 is word aligned, but src2 has no common alignment
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with it. */
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ldr data1, [src1], #4
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lsls tmp1, src2, #31 /* C=src2[1], Z=src2[0]. */
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bic src2, src2, #3
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ldr data2, [src2], #4
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bhi .Loverlap1 /* C=1, Z=0 => src2[1:0] = 0b11. */
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bcs .Loverlap2 /* C=1, Z=1 => src2[1:0] = 0b10. */
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/* (overlap3) C=0, Z=0 => src2[1:0] = 0b01. */
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.Loverlap3:
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bic tmp1, data1, #MSB
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uadd8 syndrome, data1, const_m1
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eors syndrome, tmp1, data2, S2LO #8
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sel syndrome, syndrome, const_m1
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bne 4f
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cbnz syndrome, 5f
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ldr data2, [src2], #4
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eor tmp1, tmp1, data1
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cmp tmp1, data2, S2HI #24
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bne 6f
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ldr data1, [src1], #4
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b .Loverlap3
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4:
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S2LO data2, data2, #8
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b .Lstrcmp_tail
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5:
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bics syndrome, syndrome, #MSB
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bne .Lstrcmp_done_equal
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/* We can only get here if the MSB of data1 contains 0, so
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fast-path the exit. */
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ldrb result, [src2]
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ldrd r4, r5, [sp], #16
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cfi_remember_state
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cfi_def_cfa_offset (0)
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cfi_restore (r4)
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cfi_restore (r5)
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/* R6/7 Not used in this sequence. */
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cfi_restore (r6)
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cfi_restore (r7)
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neg result, result
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bx lr
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6:
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cfi_restore_state
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S2LO data1, data1, #24
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and data2, data2, #LSB
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b .Lstrcmp_tail
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.p2align 5,,12 /* Ensure at least 3 instructions in cache line. */
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.Loverlap2:
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and tmp1, data1, const_m1, S2LO #16
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uadd8 syndrome, data1, const_m1
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eors syndrome, tmp1, data2, S2LO #16
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sel syndrome, syndrome, const_m1
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bne 4f
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cbnz syndrome, 5f
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ldr data2, [src2], #4
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eor tmp1, tmp1, data1
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cmp tmp1, data2, S2HI #16
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bne 6f
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ldr data1, [src1], #4
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b .Loverlap2
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4:
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S2LO data2, data2, #16
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b .Lstrcmp_tail
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5:
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ands syndrome, syndrome, const_m1, S2LO #16
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bne .Lstrcmp_done_equal
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ldrh data2, [src2]
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S2LO data1, data1, #16
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#ifdef __ARM_BIG_ENDIAN
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lsl data2, data2, #16
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#endif
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b .Lstrcmp_tail
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6:
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S2LO data1, data1, #16
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and data2, data2, const_m1, S2LO #16
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b .Lstrcmp_tail
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.p2align 5,,12 /* Ensure at least 3 instructions in cache line. */
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.Loverlap1:
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and tmp1, data1, #LSB
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uadd8 syndrome, data1, const_m1
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eors syndrome, tmp1, data2, S2LO #24
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sel syndrome, syndrome, const_m1
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bne 4f
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cbnz syndrome, 5f
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ldr data2, [src2], #4
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eor tmp1, tmp1, data1
|
|
cmp tmp1, data2, S2HI #8
|
|
bne 6f
|
|
ldr data1, [src1], #4
|
|
b .Loverlap1
|
|
4:
|
|
S2LO data2, data2, #24
|
|
b .Lstrcmp_tail
|
|
5:
|
|
tst syndrome, #LSB
|
|
bne .Lstrcmp_done_equal
|
|
ldr data2, [src2]
|
|
6:
|
|
S2LO data1, data1, #8
|
|
bic data2, data2, #MSB
|
|
b .Lstrcmp_tail
|
|
|
|
.Lstrcmp_done_equal:
|
|
mov result, #0
|
|
ldrd r4, r5, [sp], #16
|
|
cfi_remember_state
|
|
cfi_def_cfa_offset (0)
|
|
cfi_restore (r4)
|
|
cfi_restore (r5)
|
|
/* R6/7 not used in this sequence. */
|
|
cfi_restore (r6)
|
|
cfi_restore (r7)
|
|
bx lr
|
|
|
|
.Lstrcmp_tail:
|
|
cfi_restore_state
|
|
#ifndef __ARM_BIG_ENDIAN
|
|
rev data1, data1
|
|
rev data2, data2
|
|
/* Now everything looks big-endian... */
|
|
#endif
|
|
uadd8 tmp1, data1, const_m1
|
|
eor tmp1, data1, data2
|
|
sel syndrome, tmp1, const_m1
|
|
clz tmp1, syndrome
|
|
lsl data1, data1, tmp1
|
|
lsl data2, data2, tmp1
|
|
lsr result, data1, #24
|
|
ldrd r4, r5, [sp], #16
|
|
cfi_def_cfa_offset (0)
|
|
cfi_restore (r4)
|
|
cfi_restore (r5)
|
|
/* R6/7 not used in this sequence. */
|
|
cfi_restore (r6)
|
|
cfi_restore (r7)
|
|
sub result, result, data2, lsr #24
|
|
bx lr
|
|
END (strcmp)
|
|
libc_hidden_builtin_def (strcmp)
|