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9b7cfab180
No bug. This commit adds new optimized __memcmpeq implementation for evex. The primary optimizations are: 1) skipping the logic to find the difference of the first mismatched byte. 2) not updating src/dst addresses as the non-equals logic does not need to be reused by different areas.
49 lines
1.8 KiB
C
49 lines
1.8 KiB
C
/* Common definition for __memcmpeq ifunc selections.
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All versions must be listed in ifunc-impl-list.c.
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Copyright (C) 2017-2021 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<https://www.gnu.org/licenses/>. */
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# include <init-arch.h>
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extern __typeof (REDIRECT_NAME) OPTIMIZE1 (sse2) attribute_hidden;
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extern __typeof (REDIRECT_NAME) OPTIMIZE1 (avx2) attribute_hidden;
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extern __typeof (REDIRECT_NAME) OPTIMIZE1 (avx2_rtm) attribute_hidden;
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extern __typeof (REDIRECT_NAME) OPTIMIZE1 (evex) attribute_hidden;
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static inline void *
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IFUNC_SELECTOR (void)
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{
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const struct cpu_features* cpu_features = __get_cpu_features ();
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if (CPU_FEATURE_USABLE_P (cpu_features, AVX2)
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&& CPU_FEATURE_USABLE_P (cpu_features, BMI2)
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&& CPU_FEATURES_ARCH_P (cpu_features, AVX_Fast_Unaligned_Load))
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{
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if (CPU_FEATURE_USABLE_P (cpu_features, AVX512VL)
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&& CPU_FEATURE_USABLE_P (cpu_features, AVX512BW))
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return OPTIMIZE1 (evex);
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if (CPU_FEATURE_USABLE_P (cpu_features, RTM))
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return OPTIMIZE1 (avx2_rtm);
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if (!CPU_FEATURES_ARCH_P (cpu_features, Prefer_No_VZEROUPPER))
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return OPTIMIZE1 (avx2);
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}
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return OPTIMIZE1 (sse2);
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}
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