mirror of
https://sourceware.org/git/glibc.git
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5a82c74822
Also, change sources.redhat.com to sourceware.org.
This patch was automatically generated by running the following shell
script, which uses GNU sed, and which avoids modifying files imported
from upstream:
sed -ri '
s,(http|ftp)(://(.*\.)?(gnu|fsf|sourceware)\.org($|[^.]|\.[^a-z])),https\2,g
s,(http|ftp)(://(.*\.)?)sources\.redhat\.com($|[^.]|\.[^a-z]),https\2sourceware.org\4,g
' \
$(find $(git ls-files) -prune -type f \
! -name '*.po' \
! -name 'ChangeLog*' \
! -path COPYING ! -path COPYING.LIB \
! -path manual/fdl-1.3.texi ! -path manual/lgpl-2.1.texi \
! -path manual/texinfo.tex ! -path scripts/config.guess \
! -path scripts/config.sub ! -path scripts/install-sh \
! -path scripts/mkinstalldirs ! -path scripts/move-if-change \
! -path INSTALL ! -path locale/programs/charmap-kw.h \
! -path po/libc.pot ! -path sysdeps/gnu/errlist.c \
! '(' -name configure \
-execdir test -f configure.ac -o -f configure.in ';' ')' \
! '(' -name preconfigure \
-execdir test -f preconfigure.ac ';' ')' \
-print)
and then by running 'make dist-prepare' to regenerate files built
from the altered files, and then executing the following to cleanup:
chmod a+x sysdeps/unix/sysv/linux/riscv/configure
# Omit irrelevant whitespace and comment-only changes,
# perhaps from a slightly-different Autoconf version.
git checkout -f \
sysdeps/csky/configure \
sysdeps/hppa/configure \
sysdeps/riscv/configure \
sysdeps/unix/sysv/linux/csky/configure
# Omit changes that caused a pre-commit check to fail like this:
# remote: *** error: sysdeps/powerpc/powerpc64/ppc-mcount.S: trailing lines
git checkout -f \
sysdeps/powerpc/powerpc64/ppc-mcount.S \
sysdeps/unix/sysv/linux/s390/s390-64/syscall.S
# Omit change that caused a pre-commit check to fail like this:
# remote: *** error: sysdeps/sparc/sparc64/multiarch/memcpy-ultra3.S: last line does not end in newline
git checkout -f sysdeps/sparc/sparc64/multiarch/memcpy-ultra3.S
177 lines
3.2 KiB
ArmAsm
177 lines
3.2 KiB
ArmAsm
/* Optimized memcpy implementation for cached memory on PowerPC64/POWER8.
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Copyright (C) 2017-2019 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<https://www.gnu.org/licenses/>. */
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#include <sysdep.h>
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/* __ptr_t [r3] memcpy (__ptr_t dst [r3], __ptr_t src [r4], size_t len [r5]);
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Returns 'dst'. */
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.machine power8
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ENTRY_TOCLESS (__memcpy_power8_cached, 5)
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CALL_MCOUNT 3
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cmpldi cr7,r5,15
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bgt cr7,L(ge_16)
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andi. r9,r5,0x1
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mr r9,r3
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beq cr0,1f
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lbz r10,0(r4)
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addi r9,r3,1
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addi r4,r4,1
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stb r10,0(r3)
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1:
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andi. r10,r5,0x2
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beq cr0,2f
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lhz r10,0(r4)
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addi r9,r9,2
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addi r4,r4,2
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sth r10,-2(r9)
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2:
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andi. r10,r5,0x4
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beq cr0,3f
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lwz r10,0(r4)
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addi r9,9,4
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addi r4,4,4
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stw r10,-4(r9)
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3:
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andi. r10,r5,0x8
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beqlr cr0
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ld r10,0(r4)
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std r10,0(r9)
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blr
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.align 4
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L(ge_16):
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cmpldi cr7,r5,32
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ble cr7,L(ge_16_le_32)
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cmpldi cr7,r5,64
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ble cr7,L(gt_32_le_64)
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/* Align dst to 16 bytes. */
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andi. r9,r3,0xf
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mr r12,r3
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beq cr0,L(dst_is_align_16)
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lxvd2x v0,0,r4
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subfic r12,r9,16
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subf r5,r12,r5
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add r4,r4,r12
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add r12,r3,r12
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stxvd2x v0,0,r3
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L(dst_is_align_16):
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cmpldi cr7,r5,127
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ble cr7,L(tail_copy)
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mr r9,r12
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srdi r10,r5,7
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li r11,16
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li r6,32
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li r7,48
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mtctr r10
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clrrdi r0,r5,7
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/* Main loop, copy 128 bytes each time. */
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.align 4
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L(copy_128):
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lxvd2x v10,0,r4
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lxvd2x v11,r4,r11
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addi r8,r4,64
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addi r10,r9,64
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lxvd2x v12,r4,r6
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lxvd2x v0,r4,r7
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addi r4,r4,128
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stxvd2x v10,0,r9
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stxvd2x v11,r9,r11
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stxvd2x v12,r9,r6
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stxvd2x v0,r9,r7
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addi r9,r9,128
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lxvd2x v10,0,r8
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lxvd2x v11,r8,r11
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lxvd2x v12,r8,r6
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lxvd2x v0,r8,r7
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stxvd2x v10,0,r10
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stxvd2x v11,r10,r11
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stxvd2x v12,r10,r6
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stxvd2x v0,r10,r7
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bdnz L(copy_128)
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add r12,r12,r0
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rldicl r5,r5,0,57
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L(tail_copy):
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cmpldi cr7,r5,63
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ble cr7,L(tail_le_64)
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li r8,16
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li r10,32
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lxvd2x v10,0,r4
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li r9,48
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addi r5,r5,-64
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lxvd2x v11,r4,r8
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lxvd2x v12,r4,r10
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lxvd2x v0,r4,r9
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addi r4,r4,64
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stxvd2x v10,0,r12
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stxvd2x v11,r12,r8
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stxvd2x v12,r12,r10
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stxvd2x v0,r12,9
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addi r12,r12,64
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L(tail_le_64):
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cmpldi cr7,r5,32
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bgt cr7,L(tail_gt_32_le_64)
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cmpdi cr7,r5,0
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beqlr cr7
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addi r5,r5,-32
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li r9,16
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add r8,r4,r5
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add r10,r12,r5
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lxvd2x v12,r4,r5
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lxvd2x v0,r8,r9
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stxvd2x v12,r12,r5
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stxvd2x v0,r10,r9
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blr
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.align 4
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L(ge_16_le_32):
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addi r5,r5,-16
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lxvd2x v0,0,r4
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lxvd2x v1,r4,r5
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stxvd2x v0,0,r3
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stxvd2x v1,r3,r5
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blr
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.align 4
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L(gt_32_le_64):
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mr r12,r3
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.align 4
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L(tail_gt_32_le_64):
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li r9,16
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lxvd2x v0,0,r4
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addi r5,r5,-32
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lxvd2x v1,r4,r9
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add r8,r4,r5
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lxvd2x v2,r4,r5
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add r10,r12,r5
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lxvd2x v3,r8,r9
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stxvd2x v0,0,r12
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stxvd2x v1,r12,r9
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stxvd2x v2,r12,r5
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stxvd2x v3,r10,r9
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blr
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END_GEN_TB (__memcpy_power8_cached,TB_TOCLESS)
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