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116 lines
3.4 KiB
C
116 lines
3.4 KiB
C
/* Facilities specific to the PowerPC architecture
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Copyright (C) 2012-2013 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<http://www.gnu.org/licenses/>. */
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#ifndef _SYS_PLATFORM_PPC_H
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#define _SYS_PLATFORM_PPC_H 1
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#include <features.h>
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#include <stdint.h>
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#include <bits/ppc.h>
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/* Read the Time Base Register. */
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static inline uint64_t
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__ppc_get_timebase (void)
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{
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#if __GNUC_PREREQ (4, 8)
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return __builtin_ppc_get_timebase ();
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#else
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# ifdef __powerpc64__
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uint64_t __tb;
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/* "volatile" is necessary here, because the user expects this assembly
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isn't moved after an optimization. */
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__asm__ volatile ("mfspr %0, 268" : "=r" (__tb));
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return __tb;
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# else /* not __powerpc64__ */
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uint32_t __tbu, __tbl, __tmp; \
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__asm__ volatile ("0:\n\t"
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"mftbu %0\n\t"
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"mftbl %1\n\t"
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"mftbu %2\n\t"
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"cmpw %0, %2\n\t"
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"bne- 0b"
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: "=r" (__tbu), "=r" (__tbl), "=r" (__tmp));
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return (((uint64_t) __tbu << 32) | __tbl);
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# endif /* not __powerpc64__ */
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#endif
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}
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/* The following functions provide hints about the usage of shared processor
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resources, as defined in ISA 2.06 and newer. */
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/* Provides a hint that performance will probably be improved if shared
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resources dedicated to the executing processor are released for use by other
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processors. */
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static inline void
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__ppc_yield (void)
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{
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__asm__ volatile ("or 27,27,27");
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}
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/* Provides a hint that performance will probably be improved if shared
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resources dedicated to the executing processor are released until
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all outstanding storage accesses to caching-inhibited storage have been
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completed. */
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static inline void
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__ppc_mdoio (void)
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{
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__asm__ volatile ("or 29,29,29");
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}
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/* Provides a hint that performance will probably be improved if shared
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resources dedicated to the executing processor are released until all
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outstanding storage accesses to cacheable storage for which the data is not
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in the cache have been completed. */
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static inline void
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__ppc_mdoom (void)
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{
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__asm__ volatile ("or 30,30,30");
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}
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/* ISA 2.05 and beyond support the Program Priority Register (PPR) to adjust
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thread priorities based on lock acquisition, wait and release. The ISA
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defines the use of form 'or Rx,Rx,Rx' as the way to modify the PRI field.
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The unprivileged priorities are:
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Rx = 1 (low)
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Rx = 2 (medium)
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Rx = 6 (medium-low/normal)
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The 'or' instruction form is a nop in previous hardware, so it is safe to
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use unguarded. The default value is 'medium'.
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*/
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static inline void
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__ppc_set_ppr_med (void)
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{
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__asm__ volatile ("or 2,2,2");
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}
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static inline void
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__ppc_set_ppr_med_low (void)
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{
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__asm__ volatile ("or 6,6,6");
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}
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static inline void
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__ppc_set_ppr_low (void)
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{
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__asm__ volatile ("or 1,1,1");
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}
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#endif /* sys/platform/ppc.h */
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