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12d2dd7060
This patch optimizes the generic spinlock code. The type pthread_spinlock_t is a typedef to volatile int on all archs. Passing a volatile pointer to the atomic macros which are not mapped to the C11 atomic builtins can lead to extra stores and loads to stack if such a macro creates a temporary variable by using "__typeof (*(mem)) tmp;". Thus, those macros which are used by spinlock code - atomic_exchange_acquire, atomic_load_relaxed, atomic_compare_exchange_weak - have to be adjusted. According to the comment from Szabolcs Nagy, the type of a cast expression is unqualified (see http://www.open-std.org/jtc1/sc22/wg14/www/docs/dr_423.htm): __typeof ((__typeof (*(mem)) *(mem)) tmp; Thus from spinlock perspective the variable tmp is of type int instead of type volatile int. This patch adjusts those macros in include/atomic.h. With this construct GCC >= 5 omits the extra stores and loads. The atomic macros are replaced by the C11 like atomic macros and thus the code is aligned to it. The pthread_spin_unlock implementation is now using release memory order instead of sequentially consistent memory order. The issue with passed volatile int pointers applies to the C11 like atomic macros as well as the ones used before. I've added a glibc_likely hint to the first atomic exchange in pthread_spin_lock in order to return immediately to the caller if the lock is free. Without the hint, there is an additional jump if the lock is free. I've added the atomic_spin_nop macro within the loop of plain reads. The plain reads are also realized by C11 like atomic_load_relaxed macro. The new define ATOMIC_EXCHANGE_USES_CAS determines if the first try to acquire the spinlock in pthread_spin_lock or pthread_spin_trylock is an exchange or a CAS. This is defined in atomic-machine.h for all architectures. The define SPIN_LOCK_READS_BETWEEN_CMPXCHG is now removed. There is no technical reason for throwing in a CAS every now and then, and so far we have no evidence that it can improve performance. If that would be the case, we have to adjust other spin-waiting loops elsewhere, too! Using a CAS loop without plain reads is not a good idea on many targets and wasn't used by one. Thus there is now no option to do so. Architectures are now using the generic spinlock automatically if they do not provide an own implementation. Thus the pthread_spin_lock.c files in sysdeps folder are deleted. ChangeLog: * NEWS: Mention new spinlock implementation. * include/atomic.h: (__atomic_val_bysize): Cast type to omit volatile qualifier. (atomic_exchange_acq): Likewise. (atomic_load_relaxed): Likewise. (ATOMIC_EXCHANGE_USES_CAS): Check definition. * nptl/pthread_spin_init.c (pthread_spin_init): Use atomic_store_relaxed. * nptl/pthread_spin_lock.c (pthread_spin_lock): Use C11-like atomic macros. * nptl/pthread_spin_trylock.c (pthread_spin_trylock): Likewise. * nptl/pthread_spin_unlock.c (pthread_spin_unlock): Use atomic_store_release. * sysdeps/aarch64/nptl/pthread_spin_lock.c: Delete File. * sysdeps/arm/nptl/pthread_spin_lock.c: Likewise. * sysdeps/hppa/nptl/pthread_spin_lock.c: Likewise. * sysdeps/m68k/nptl/pthread_spin_lock.c: Likewise. * sysdeps/microblaze/nptl/pthread_spin_lock.c: Likewise. * sysdeps/mips/nptl/pthread_spin_lock.c: Likewise. * sysdeps/nios2/nptl/pthread_spin_lock.c: Likewise. * sysdeps/aarch64/atomic-machine.h (ATOMIC_EXCHANGE_USES_CAS): Define. * sysdeps/alpha/atomic-machine.h: Likewise. * sysdeps/arm/atomic-machine.h: Likewise. * sysdeps/i386/atomic-machine.h: Likewise. * sysdeps/ia64/atomic-machine.h: Likewise. * sysdeps/m68k/coldfire/atomic-machine.h: Likewise. * sysdeps/m68k/m680x0/m68020/atomic-machine.h: Likewise. * sysdeps/microblaze/atomic-machine.h: Likewise. * sysdeps/mips/atomic-machine.h: Likewise. * sysdeps/powerpc/powerpc32/atomic-machine.h: Likewise. * sysdeps/powerpc/powerpc64/atomic-machine.h: Likewise. * sysdeps/s390/atomic-machine.h: Likewise. * sysdeps/sparc/sparc32/atomic-machine.h: Likewise. * sysdeps/sparc/sparc32/sparcv9/atomic-machine.h: Likewise. * sysdeps/sparc/sparc64/atomic-machine.h: Likewise. * sysdeps/tile/tilegx/atomic-machine.h: Likewise. * sysdeps/tile/tilepro/atomic-machine.h: Likewise. * sysdeps/unix/sysv/linux/hppa/atomic-machine.h: Likewise. * sysdeps/unix/sysv/linux/m68k/coldfire/atomic-machine.h: Likewise. * sysdeps/unix/sysv/linux/nios2/atomic-machine.h: Likewise. * sysdeps/unix/sysv/linux/sh/atomic-machine.h: Likewise. * sysdeps/x86_64/atomic-machine.h: Likewise.
483 lines
18 KiB
C
483 lines
18 KiB
C
/* Copyright (C) 2002-2017 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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Contributed by Ulrich Drepper <drepper@redhat.com>, 2002.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<http://www.gnu.org/licenses/>. */
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#ifndef _X86_64_ATOMIC_MACHINE_H
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#define _X86_64_ATOMIC_MACHINE_H 1
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#include <stdint.h>
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#include <tls.h> /* For tcbhead_t. */
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#include <libc-pointer-arith.h> /* For cast_to_integer. */
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typedef int8_t atomic8_t;
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typedef uint8_t uatomic8_t;
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typedef int_fast8_t atomic_fast8_t;
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typedef uint_fast8_t uatomic_fast8_t;
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typedef int16_t atomic16_t;
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typedef uint16_t uatomic16_t;
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typedef int_fast16_t atomic_fast16_t;
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typedef uint_fast16_t uatomic_fast16_t;
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typedef int32_t atomic32_t;
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typedef uint32_t uatomic32_t;
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typedef int_fast32_t atomic_fast32_t;
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typedef uint_fast32_t uatomic_fast32_t;
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typedef int64_t atomic64_t;
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typedef uint64_t uatomic64_t;
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typedef int_fast64_t atomic_fast64_t;
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typedef uint_fast64_t uatomic_fast64_t;
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typedef intptr_t atomicptr_t;
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typedef uintptr_t uatomicptr_t;
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typedef intmax_t atomic_max_t;
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typedef uintmax_t uatomic_max_t;
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#ifndef LOCK_PREFIX
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# ifdef UP
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# define LOCK_PREFIX /* nothing */
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# else
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# define LOCK_PREFIX "lock;"
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# endif
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#endif
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#define __HAVE_64B_ATOMICS 1
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#define USE_ATOMIC_COMPILER_BUILTINS 1
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#define ATOMIC_EXCHANGE_USES_CAS 0
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#define atomic_compare_and_exchange_val_acq(mem, newval, oldval) \
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__sync_val_compare_and_swap (mem, oldval, newval)
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#define atomic_compare_and_exchange_bool_acq(mem, newval, oldval) \
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(! __sync_bool_compare_and_swap (mem, oldval, newval))
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#define __arch_c_compare_and_exchange_val_8_acq(mem, newval, oldval) \
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({ __typeof (*mem) ret; \
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__asm __volatile ("cmpl $0, %%fs:%P5\n\t" \
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"je 0f\n\t" \
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"lock\n" \
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"0:\tcmpxchgb %b2, %1" \
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: "=a" (ret), "=m" (*mem) \
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: "q" (newval), "m" (*mem), "0" (oldval), \
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"i" (offsetof (tcbhead_t, multiple_threads))); \
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ret; })
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#define __arch_c_compare_and_exchange_val_16_acq(mem, newval, oldval) \
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({ __typeof (*mem) ret; \
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__asm __volatile ("cmpl $0, %%fs:%P5\n\t" \
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"je 0f\n\t" \
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"lock\n" \
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"0:\tcmpxchgw %w2, %1" \
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: "=a" (ret), "=m" (*mem) \
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: "q" (newval), "m" (*mem), "0" (oldval), \
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"i" (offsetof (tcbhead_t, multiple_threads))); \
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ret; })
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#define __arch_c_compare_and_exchange_val_32_acq(mem, newval, oldval) \
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({ __typeof (*mem) ret; \
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__asm __volatile ("cmpl $0, %%fs:%P5\n\t" \
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"je 0f\n\t" \
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"lock\n" \
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"0:\tcmpxchgl %2, %1" \
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: "=a" (ret), "=m" (*mem) \
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: "q" (newval), "m" (*mem), "0" (oldval), \
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"i" (offsetof (tcbhead_t, multiple_threads))); \
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ret; })
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#define __arch_c_compare_and_exchange_val_64_acq(mem, newval, oldval) \
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({ __typeof (*mem) ret; \
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__asm __volatile ("cmpl $0, %%fs:%P5\n\t" \
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"je 0f\n\t" \
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"lock\n" \
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"0:\tcmpxchgq %q2, %1" \
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: "=a" (ret), "=m" (*mem) \
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: "q" ((atomic64_t) cast_to_integer (newval)), \
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"m" (*mem), \
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"0" ((atomic64_t) cast_to_integer (oldval)), \
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"i" (offsetof (tcbhead_t, multiple_threads))); \
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ret; })
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/* Note that we need no lock prefix. */
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#define atomic_exchange_acq(mem, newvalue) \
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({ __typeof (*mem) result; \
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if (sizeof (*mem) == 1) \
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__asm __volatile ("xchgb %b0, %1" \
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: "=q" (result), "=m" (*mem) \
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: "0" (newvalue), "m" (*mem)); \
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else if (sizeof (*mem) == 2) \
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__asm __volatile ("xchgw %w0, %1" \
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: "=r" (result), "=m" (*mem) \
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: "0" (newvalue), "m" (*mem)); \
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else if (sizeof (*mem) == 4) \
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__asm __volatile ("xchgl %0, %1" \
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: "=r" (result), "=m" (*mem) \
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: "0" (newvalue), "m" (*mem)); \
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else \
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__asm __volatile ("xchgq %q0, %1" \
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: "=r" (result), "=m" (*mem) \
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: "0" ((atomic64_t) cast_to_integer (newvalue)), \
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"m" (*mem)); \
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result; })
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#define __arch_exchange_and_add_body(lock, mem, value) \
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({ __typeof (*mem) result; \
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if (sizeof (*mem) == 1) \
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__asm __volatile (lock "xaddb %b0, %1" \
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: "=q" (result), "=m" (*mem) \
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: "0" (value), "m" (*mem), \
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"i" (offsetof (tcbhead_t, multiple_threads))); \
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else if (sizeof (*mem) == 2) \
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__asm __volatile (lock "xaddw %w0, %1" \
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: "=r" (result), "=m" (*mem) \
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: "0" (value), "m" (*mem), \
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"i" (offsetof (tcbhead_t, multiple_threads))); \
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else if (sizeof (*mem) == 4) \
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__asm __volatile (lock "xaddl %0, %1" \
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: "=r" (result), "=m" (*mem) \
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: "0" (value), "m" (*mem), \
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"i" (offsetof (tcbhead_t, multiple_threads))); \
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else \
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__asm __volatile (lock "xaddq %q0, %1" \
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: "=r" (result), "=m" (*mem) \
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: "0" ((atomic64_t) cast_to_integer (value)), \
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"m" (*mem), \
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"i" (offsetof (tcbhead_t, multiple_threads))); \
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result; })
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#define atomic_exchange_and_add(mem, value) \
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__sync_fetch_and_add (mem, value)
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#define __arch_exchange_and_add_cprefix \
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"cmpl $0, %%fs:%P4\n\tje 0f\n\tlock\n0:\t"
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#define catomic_exchange_and_add(mem, value) \
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__arch_exchange_and_add_body (__arch_exchange_and_add_cprefix, mem, value)
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#define __arch_add_body(lock, pfx, mem, value) \
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do { \
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if (__builtin_constant_p (value) && (value) == 1) \
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pfx##_increment (mem); \
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else if (__builtin_constant_p (value) && (value) == -1) \
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pfx##_decrement (mem); \
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else if (sizeof (*mem) == 1) \
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__asm __volatile (lock "addb %b1, %0" \
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: "=m" (*mem) \
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: "iq" (value), "m" (*mem), \
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"i" (offsetof (tcbhead_t, multiple_threads))); \
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else if (sizeof (*mem) == 2) \
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__asm __volatile (lock "addw %w1, %0" \
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: "=m" (*mem) \
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: "ir" (value), "m" (*mem), \
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"i" (offsetof (tcbhead_t, multiple_threads))); \
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else if (sizeof (*mem) == 4) \
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__asm __volatile (lock "addl %1, %0" \
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: "=m" (*mem) \
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: "ir" (value), "m" (*mem), \
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"i" (offsetof (tcbhead_t, multiple_threads))); \
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else \
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__asm __volatile (lock "addq %q1, %0" \
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: "=m" (*mem) \
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: "ir" ((atomic64_t) cast_to_integer (value)), \
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"m" (*mem), \
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"i" (offsetof (tcbhead_t, multiple_threads))); \
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} while (0)
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#define atomic_add(mem, value) \
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__arch_add_body (LOCK_PREFIX, atomic, mem, value)
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#define __arch_add_cprefix \
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"cmpl $0, %%fs:%P3\n\tje 0f\n\tlock\n0:\t"
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#define catomic_add(mem, value) \
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__arch_add_body (__arch_add_cprefix, catomic, mem, value)
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#define atomic_add_negative(mem, value) \
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({ unsigned char __result; \
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if (sizeof (*mem) == 1) \
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__asm __volatile (LOCK_PREFIX "addb %b2, %0; sets %1" \
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: "=m" (*mem), "=qm" (__result) \
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: "iq" (value), "m" (*mem)); \
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else if (sizeof (*mem) == 2) \
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__asm __volatile (LOCK_PREFIX "addw %w2, %0; sets %1" \
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: "=m" (*mem), "=qm" (__result) \
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: "ir" (value), "m" (*mem)); \
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else if (sizeof (*mem) == 4) \
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__asm __volatile (LOCK_PREFIX "addl %2, %0; sets %1" \
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: "=m" (*mem), "=qm" (__result) \
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: "ir" (value), "m" (*mem)); \
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else \
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__asm __volatile (LOCK_PREFIX "addq %q2, %0; sets %1" \
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: "=m" (*mem), "=qm" (__result) \
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: "ir" ((atomic64_t) cast_to_integer (value)), \
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"m" (*mem)); \
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__result; })
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#define atomic_add_zero(mem, value) \
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({ unsigned char __result; \
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if (sizeof (*mem) == 1) \
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__asm __volatile (LOCK_PREFIX "addb %b2, %0; setz %1" \
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: "=m" (*mem), "=qm" (__result) \
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: "iq" (value), "m" (*mem)); \
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else if (sizeof (*mem) == 2) \
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__asm __volatile (LOCK_PREFIX "addw %w2, %0; setz %1" \
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: "=m" (*mem), "=qm" (__result) \
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: "ir" (value), "m" (*mem)); \
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else if (sizeof (*mem) == 4) \
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__asm __volatile (LOCK_PREFIX "addl %2, %0; setz %1" \
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: "=m" (*mem), "=qm" (__result) \
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: "ir" (value), "m" (*mem)); \
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else \
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__asm __volatile (LOCK_PREFIX "addq %q2, %0; setz %1" \
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: "=m" (*mem), "=qm" (__result) \
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: "ir" ((atomic64_t) cast_to_integer (value)), \
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"m" (*mem)); \
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__result; })
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#define __arch_increment_body(lock, mem) \
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do { \
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if (sizeof (*mem) == 1) \
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__asm __volatile (lock "incb %b0" \
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: "=m" (*mem) \
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: "m" (*mem), \
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"i" (offsetof (tcbhead_t, multiple_threads))); \
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else if (sizeof (*mem) == 2) \
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__asm __volatile (lock "incw %w0" \
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: "=m" (*mem) \
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: "m" (*mem), \
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"i" (offsetof (tcbhead_t, multiple_threads))); \
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else if (sizeof (*mem) == 4) \
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__asm __volatile (lock "incl %0" \
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: "=m" (*mem) \
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: "m" (*mem), \
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"i" (offsetof (tcbhead_t, multiple_threads))); \
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else \
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__asm __volatile (lock "incq %q0" \
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: "=m" (*mem) \
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: "m" (*mem), \
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"i" (offsetof (tcbhead_t, multiple_threads))); \
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} while (0)
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#define atomic_increment(mem) __arch_increment_body (LOCK_PREFIX, mem)
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#define __arch_increment_cprefix \
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"cmpl $0, %%fs:%P2\n\tje 0f\n\tlock\n0:\t"
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#define catomic_increment(mem) \
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__arch_increment_body (__arch_increment_cprefix, mem)
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#define atomic_increment_and_test(mem) \
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({ unsigned char __result; \
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if (sizeof (*mem) == 1) \
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__asm __volatile (LOCK_PREFIX "incb %b0; sete %1" \
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: "=m" (*mem), "=qm" (__result) \
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: "m" (*mem)); \
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else if (sizeof (*mem) == 2) \
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__asm __volatile (LOCK_PREFIX "incw %w0; sete %1" \
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: "=m" (*mem), "=qm" (__result) \
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: "m" (*mem)); \
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else if (sizeof (*mem) == 4) \
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__asm __volatile (LOCK_PREFIX "incl %0; sete %1" \
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: "=m" (*mem), "=qm" (__result) \
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: "m" (*mem)); \
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else \
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__asm __volatile (LOCK_PREFIX "incq %q0; sete %1" \
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: "=m" (*mem), "=qm" (__result) \
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: "m" (*mem)); \
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__result; })
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#define __arch_decrement_body(lock, mem) \
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do { \
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if (sizeof (*mem) == 1) \
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__asm __volatile (lock "decb %b0" \
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: "=m" (*mem) \
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: "m" (*mem), \
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"i" (offsetof (tcbhead_t, multiple_threads))); \
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else if (sizeof (*mem) == 2) \
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__asm __volatile (lock "decw %w0" \
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: "=m" (*mem) \
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: "m" (*mem), \
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"i" (offsetof (tcbhead_t, multiple_threads))); \
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else if (sizeof (*mem) == 4) \
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__asm __volatile (lock "decl %0" \
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: "=m" (*mem) \
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: "m" (*mem), \
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"i" (offsetof (tcbhead_t, multiple_threads))); \
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else \
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__asm __volatile (lock "decq %q0" \
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: "=m" (*mem) \
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: "m" (*mem), \
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"i" (offsetof (tcbhead_t, multiple_threads))); \
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} while (0)
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#define atomic_decrement(mem) __arch_decrement_body (LOCK_PREFIX, mem)
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#define __arch_decrement_cprefix \
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"cmpl $0, %%fs:%P2\n\tje 0f\n\tlock\n0:\t"
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#define catomic_decrement(mem) \
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__arch_decrement_body (__arch_decrement_cprefix, mem)
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#define atomic_decrement_and_test(mem) \
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({ unsigned char __result; \
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if (sizeof (*mem) == 1) \
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__asm __volatile (LOCK_PREFIX "decb %b0; sete %1" \
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: "=m" (*mem), "=qm" (__result) \
|
|
: "m" (*mem)); \
|
|
else if (sizeof (*mem) == 2) \
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|
__asm __volatile (LOCK_PREFIX "decw %w0; sete %1" \
|
|
: "=m" (*mem), "=qm" (__result) \
|
|
: "m" (*mem)); \
|
|
else if (sizeof (*mem) == 4) \
|
|
__asm __volatile (LOCK_PREFIX "decl %0; sete %1" \
|
|
: "=m" (*mem), "=qm" (__result) \
|
|
: "m" (*mem)); \
|
|
else \
|
|
__asm __volatile (LOCK_PREFIX "decq %q0; sete %1" \
|
|
: "=m" (*mem), "=qm" (__result) \
|
|
: "m" (*mem)); \
|
|
__result; })
|
|
|
|
|
|
#define atomic_bit_set(mem, bit) \
|
|
do { \
|
|
if (sizeof (*mem) == 1) \
|
|
__asm __volatile (LOCK_PREFIX "orb %b2, %0" \
|
|
: "=m" (*mem) \
|
|
: "m" (*mem), "iq" (1L << (bit))); \
|
|
else if (sizeof (*mem) == 2) \
|
|
__asm __volatile (LOCK_PREFIX "orw %w2, %0" \
|
|
: "=m" (*mem) \
|
|
: "m" (*mem), "ir" (1L << (bit))); \
|
|
else if (sizeof (*mem) == 4) \
|
|
__asm __volatile (LOCK_PREFIX "orl %2, %0" \
|
|
: "=m" (*mem) \
|
|
: "m" (*mem), "ir" (1L << (bit))); \
|
|
else if (__builtin_constant_p (bit) && (bit) < 32) \
|
|
__asm __volatile (LOCK_PREFIX "orq %2, %0" \
|
|
: "=m" (*mem) \
|
|
: "m" (*mem), "i" (1L << (bit))); \
|
|
else \
|
|
__asm __volatile (LOCK_PREFIX "orq %q2, %0" \
|
|
: "=m" (*mem) \
|
|
: "m" (*mem), "r" (1UL << (bit))); \
|
|
} while (0)
|
|
|
|
|
|
#define atomic_bit_test_set(mem, bit) \
|
|
({ unsigned char __result; \
|
|
if (sizeof (*mem) == 1) \
|
|
__asm __volatile (LOCK_PREFIX "btsb %3, %1; setc %0" \
|
|
: "=q" (__result), "=m" (*mem) \
|
|
: "m" (*mem), "iq" (bit)); \
|
|
else if (sizeof (*mem) == 2) \
|
|
__asm __volatile (LOCK_PREFIX "btsw %3, %1; setc %0" \
|
|
: "=q" (__result), "=m" (*mem) \
|
|
: "m" (*mem), "ir" (bit)); \
|
|
else if (sizeof (*mem) == 4) \
|
|
__asm __volatile (LOCK_PREFIX "btsl %3, %1; setc %0" \
|
|
: "=q" (__result), "=m" (*mem) \
|
|
: "m" (*mem), "ir" (bit)); \
|
|
else \
|
|
__asm __volatile (LOCK_PREFIX "btsq %3, %1; setc %0" \
|
|
: "=q" (__result), "=m" (*mem) \
|
|
: "m" (*mem), "ir" (bit)); \
|
|
__result; })
|
|
|
|
|
|
#define atomic_spin_nop() asm ("rep; nop")
|
|
|
|
|
|
#define __arch_and_body(lock, mem, mask) \
|
|
do { \
|
|
if (sizeof (*mem) == 1) \
|
|
__asm __volatile (lock "andb %b1, %0" \
|
|
: "=m" (*mem) \
|
|
: "iq" (mask), "m" (*mem), \
|
|
"i" (offsetof (tcbhead_t, multiple_threads))); \
|
|
else if (sizeof (*mem) == 2) \
|
|
__asm __volatile (lock "andw %w1, %0" \
|
|
: "=m" (*mem) \
|
|
: "ir" (mask), "m" (*mem), \
|
|
"i" (offsetof (tcbhead_t, multiple_threads))); \
|
|
else if (sizeof (*mem) == 4) \
|
|
__asm __volatile (lock "andl %1, %0" \
|
|
: "=m" (*mem) \
|
|
: "ir" (mask), "m" (*mem), \
|
|
"i" (offsetof (tcbhead_t, multiple_threads))); \
|
|
else \
|
|
__asm __volatile (lock "andq %q1, %0" \
|
|
: "=m" (*mem) \
|
|
: "ir" (mask), "m" (*mem), \
|
|
"i" (offsetof (tcbhead_t, multiple_threads))); \
|
|
} while (0)
|
|
|
|
#define __arch_cprefix \
|
|
"cmpl $0, %%fs:%P3\n\tje 0f\n\tlock\n0:\t"
|
|
|
|
#define atomic_and(mem, mask) __arch_and_body (LOCK_PREFIX, mem, mask)
|
|
|
|
#define catomic_and(mem, mask) __arch_and_body (__arch_cprefix, mem, mask)
|
|
|
|
|
|
#define __arch_or_body(lock, mem, mask) \
|
|
do { \
|
|
if (sizeof (*mem) == 1) \
|
|
__asm __volatile (lock "orb %b1, %0" \
|
|
: "=m" (*mem) \
|
|
: "iq" (mask), "m" (*mem), \
|
|
"i" (offsetof (tcbhead_t, multiple_threads))); \
|
|
else if (sizeof (*mem) == 2) \
|
|
__asm __volatile (lock "orw %w1, %0" \
|
|
: "=m" (*mem) \
|
|
: "ir" (mask), "m" (*mem), \
|
|
"i" (offsetof (tcbhead_t, multiple_threads))); \
|
|
else if (sizeof (*mem) == 4) \
|
|
__asm __volatile (lock "orl %1, %0" \
|
|
: "=m" (*mem) \
|
|
: "ir" (mask), "m" (*mem), \
|
|
"i" (offsetof (tcbhead_t, multiple_threads))); \
|
|
else \
|
|
__asm __volatile (lock "orq %q1, %0" \
|
|
: "=m" (*mem) \
|
|
: "ir" (mask), "m" (*mem), \
|
|
"i" (offsetof (tcbhead_t, multiple_threads))); \
|
|
} while (0)
|
|
|
|
#define atomic_or(mem, mask) __arch_or_body (LOCK_PREFIX, mem, mask)
|
|
|
|
#define catomic_or(mem, mask) __arch_or_body (__arch_cprefix, mem, mask)
|
|
|
|
/* We don't use mfence because it is supposedly slower due to having to
|
|
provide stronger guarantees (e.g., regarding self-modifying code). */
|
|
#define atomic_full_barrier() \
|
|
__asm __volatile (LOCK_PREFIX "orl $0, (%%rsp)" ::: "memory")
|
|
#define atomic_read_barrier() __asm ("" ::: "memory")
|
|
#define atomic_write_barrier() __asm ("" ::: "memory")
|
|
|
|
#endif /* atomic-machine.h */
|