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f9646d138f
As per other architectures. I have checked on a armv8 hardware with the following configurations: arm-linux-gnueabihf (gcc built with --with-float=hard --with-cpu=arm926ej-s) armv5-linux-gnueabihf (-march=armv5te -mfpu=vfpv3) armv7-linux-gnueabihf (-march=armv7-a -mfpu=vfpv3) armv7-thumb-linux-gnueabihf (-march=armv7-a -mfpu=vfpv3 -mthumb) armv7-neon-linux-gnueabihf (-march=armv7-a -mfpu=neon) armv7-neonhard-linux-gnueabihf (-march=armv7-a -mfpu=neon -mfloat-abi=hard) Without any regression. I haven't dig into the code, but since Linux atomic-machine.h handle pre-ARMv6 and ARMv6 I expect the compiler might have some small room to optimize. The code size also improves is most of the configurations: * master text data bss dec hex filename 1727801 9720 37928 1775449 1b1759 arm-linux-gnueabihf/libc.so 1691729 9720 37928 1739377 1a8a71 arm-linux-gnueabihf-armv7-disable-multi-arch/libc.so 1725509 9720 37928 1773157 1b0e65 armv5-linux-gnueabihf/libc.so 1700757 9720 37928 1748405 1aadb5 armv6-linux-gnueabihf/libc.so 1698973 9720 37928 1746621 1aa6bd armv6t2-linux-gnueabihf/libc.so 1695481 9752 37928 1743161 1a9939 armv7-linux-gnueabihf/libc.so 1692917 9744 37928 1740589 1a8f2d armv7-neonhard-linux-gnueabihf/libc.so 1692917 9744 37928 1740589 1a8f2d armv7-neon-linux-gnueabihf/libc.so 1225353 9752 37928 1273033 136cc9 armv7-thumb-linux-gnueabihf/libc.so * patched text data bss dec hex filename 1726805 9720 37928 1774453 1b1375 arm-linux-gnueabihf/libc.so 1689321 9720 37928 1736969 1a8109 arm-linux-gnueabihf-armv7-disable-multi-arch/libc.so 1724433 9720 37928 1772081 1b0a31 armv5-linux-gnueabihf/libc.so 1698301 9720 37928 1745949 1aa41d armv6-linux-gnueabihf/libc.so 1696525 9720 37928 1744173 1a9d2d armv6t2-linux-gnueabihf/libc.so 1693009 9752 37928 1740689 1a8f91 armv7-linux-gnueabihf/libc.so 1690493 9744 37928 1738165 1a85b5 armv7-neonhard-linux-gnueabihf/libc.so 1690493 9744 37928 1738165 1a85b5 armv7-neon-linux-gnueabihf/libc.so 1223837 9752 37928 1271517 1366dd armv7-thumb-linux-gnueabihf/libc.so The idea is eventually move all architectures to use compiler builtins. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Tested-by: Aurelien Jarno <aurelien@aurel32.net>
139 lines
5.5 KiB
C
139 lines
5.5 KiB
C
/* Atomic operations. Pure ARM version.
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Copyright (C) 2002-2022 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library. If not, see
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<https://www.gnu.org/licenses/>. */
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#define __HAVE_64B_ATOMICS 0
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#define USE_ATOMIC_COMPILER_BUILTINS 1
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#define ATOMIC_EXCHANGE_USES_CAS 1
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void __arm_link_error (void);
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#ifdef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4
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# define atomic_full_barrier() __sync_synchronize ()
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#else
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# define atomic_full_barrier() __arm_assisted_full_barrier ()
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#endif
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/* An OS-specific atomic-machine.h file will define this macro if
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the OS can provide something. If not, we'll fail to build
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with a compiler that doesn't supply the operation. */
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#ifndef __arm_assisted_full_barrier
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# define __arm_assisted_full_barrier() __arm_link_error()
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#endif
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/* Use the atomic builtins provided by GCC in case the backend provides
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a pattern to do this efficiently. */
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#ifdef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4
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# define atomic_exchange_acq(mem, value) \
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__atomic_val_bysize (__arch_exchange, int, mem, value, __ATOMIC_ACQUIRE)
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# define atomic_exchange_rel(mem, value) \
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__atomic_val_bysize (__arch_exchange, int, mem, value, __ATOMIC_RELEASE)
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/* Atomic exchange (without compare). */
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# define __arch_exchange_8_int(mem, newval, model) \
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(__arm_link_error (), (typeof (*mem)) 0)
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# define __arch_exchange_16_int(mem, newval, model) \
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(__arm_link_error (), (typeof (*mem)) 0)
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# define __arch_exchange_32_int(mem, newval, model) \
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__atomic_exchange_n (mem, newval, model)
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# define __arch_exchange_64_int(mem, newval, model) \
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(__arm_link_error (), (typeof (*mem)) 0)
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/* Compare and exchange with "acquire" semantics, ie barrier after. */
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# define atomic_compare_and_exchange_bool_acq(mem, new, old) \
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__atomic_bool_bysize (__arch_compare_and_exchange_bool, int, \
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mem, new, old, __ATOMIC_ACQUIRE)
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# define atomic_compare_and_exchange_val_acq(mem, new, old) \
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__atomic_val_bysize (__arch_compare_and_exchange_val, int, \
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mem, new, old, __ATOMIC_ACQUIRE)
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/* Compare and exchange with "release" semantics, ie barrier before. */
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# define atomic_compare_and_exchange_val_rel(mem, new, old) \
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__atomic_val_bysize (__arch_compare_and_exchange_val, int, \
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mem, new, old, __ATOMIC_RELEASE)
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/* Compare and exchange.
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For all "bool" routines, we return FALSE if exchange succesful. */
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# define __arch_compare_and_exchange_bool_8_int(mem, newval, oldval, model) \
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({__arm_link_error (); 0; })
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# define __arch_compare_and_exchange_bool_16_int(mem, newval, oldval, model) \
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({__arm_link_error (); 0; })
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# define __arch_compare_and_exchange_bool_32_int(mem, newval, oldval, model) \
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({ \
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typeof (*mem) __oldval = (oldval); \
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!__atomic_compare_exchange_n (mem, (void *) &__oldval, newval, 0, \
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model, __ATOMIC_RELAXED); \
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})
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# define __arch_compare_and_exchange_bool_64_int(mem, newval, oldval, model) \
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({__arm_link_error (); 0; })
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# define __arch_compare_and_exchange_val_8_int(mem, newval, oldval, model) \
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({__arm_link_error (); oldval; })
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# define __arch_compare_and_exchange_val_16_int(mem, newval, oldval, model) \
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({__arm_link_error (); oldval; })
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# define __arch_compare_and_exchange_val_32_int(mem, newval, oldval, model) \
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({ \
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typeof (*mem) __oldval = (oldval); \
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__atomic_compare_exchange_n (mem, (void *) &__oldval, newval, 0, \
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model, __ATOMIC_RELAXED); \
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__oldval; \
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})
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# define __arch_compare_and_exchange_val_64_int(mem, newval, oldval, model) \
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({__arm_link_error (); oldval; })
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#else
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# define __arch_compare_and_exchange_val_32_acq(mem, newval, oldval) \
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__arm_assisted_compare_and_exchange_val_32_acq ((mem), (newval), (oldval))
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#endif
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#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4
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/* We don't support atomic operations on any non-word types.
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So make them link errors. */
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# define __arch_compare_and_exchange_val_8_acq(mem, newval, oldval) \
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({ __arm_link_error (); oldval; })
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# define __arch_compare_and_exchange_val_16_acq(mem, newval, oldval) \
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({ __arm_link_error (); oldval; })
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# define __arch_compare_and_exchange_val_64_acq(mem, newval, oldval) \
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({ __arm_link_error (); oldval; })
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#endif
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/* An OS-specific atomic-machine.h file will define this macro if
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the OS can provide something. If not, we'll fail to build
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with a compiler that doesn't supply the operation. */
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#ifndef __arm_assisted_compare_and_exchange_val_32_acq
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# define __arm_assisted_compare_and_exchange_val_32_acq(mem, newval, oldval) \
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({ __arm_link_error (); oldval; })
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#endif
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