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81cb7a0b2b
This semi-mechanical patch removes all uses and definitions of the
sfi_breg, sfi_pld, and sfi_sp macros from various ARM-specific
assembly files. These were only used by NaCl.
* sysdeps/arm/sysdep.h
(ARM_SFI_MACROS, sfi_breg, sfi_pld, sfi_sp): Delete definitions.
* sysdeps/arm/__longjmp.S, sysdeps/arm/add_n.S
* sysdeps/arm/addmul_1.S, sysdeps/arm/arm-mcount.S
* sysdeps/arm/armv6/rawmemchr.S, sysdeps/arm/armv6/strchr.S
* sysdeps/arm/armv6/strcpy.S, sysdeps/arm/armv6/strlen.S
* sysdeps/arm/armv6/strrchr.S, sysdeps/arm/armv6t2/memchr.S
* sysdeps/arm/armv6t2/strlen.S
* sysdeps/arm/armv7/multiarch/memcpy_impl.S
* sysdeps/arm/armv7/strcmp.S, sysdeps/arm/dl-tlsdesc.S
* sysdeps/arm/memcpy.S, sysdeps/arm/memmove.S
* sysdeps/arm/memset.S, sysdeps/arm/setjmp.S
* sysdeps/arm/strlen.S, sysdeps/arm/submul_1.S:
Remove all uses of sfi_breg, sfi_pld, and sfi_sp.
321 lines
7.3 KiB
ArmAsm
321 lines
7.3 KiB
ArmAsm
/* Copyright (C) 2006-2017 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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Contributed by MontaVista Software, Inc. (written by Nicolas Pitre)
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library. If not, see
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<http://www.gnu.org/licenses/>. */
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/* Thumb requires excessive IT insns here. */
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#define NO_THUMB
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#include <sysdep.h>
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#include <arm-features.h>
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/*
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* Data preload for architectures that support it (ARM V5TE and above)
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*/
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#if (!defined (__ARM_ARCH_2__) && !defined (__ARM_ARCH_3__) \
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&& !defined (__ARM_ARCH_3M__) && !defined (__ARM_ARCH_4__) \
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&& !defined (__ARM_ARCH_4T__) && !defined (__ARM_ARCH_5__) \
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&& !defined (__ARM_ARCH_5T__))
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#define PLD(code...) code
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#else
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#define PLD(code...)
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#endif
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/*
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* This can be used to enable code to cacheline align the source pointer.
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* Experiments on tested architectures (StrongARM and XScale) didn't show
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* this a worthwhile thing to do. That might be different in the future.
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*/
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//#define CALGN(code...) code
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#define CALGN(code...)
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/*
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* Endian independent macros for shifting bytes within registers.
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*/
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#ifndef __ARMEB__
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#define PULL lsr
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#define PUSH lsl
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#else
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#define PULL lsl
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#define PUSH lsr
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#endif
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.text
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.syntax unified
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/* Prototype: void *memcpy(void *dest, const void *src, size_t n); */
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ENTRY(memcpy)
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push {r0, r4, lr}
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cfi_adjust_cfa_offset (12)
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cfi_rel_offset (r4, 4)
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cfi_rel_offset (lr, 8)
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cfi_remember_state
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subs r2, r2, #4
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blt 8f
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ands ip, r0, #3
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PLD( pld [r1, #0] )
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bne 9f
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ands ip, r1, #3
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bne 10f
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1: subs r2, r2, #(28)
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push {r5 - r8}
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cfi_adjust_cfa_offset (16)
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cfi_rel_offset (r5, 0)
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cfi_rel_offset (r6, 4)
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cfi_rel_offset (r7, 8)
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cfi_rel_offset (r8, 12)
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blt 5f
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CALGN( ands ip, r1, #31 )
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CALGN( rsb r3, ip, #32 )
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CALGN( sbcsne r4, r3, r2 ) @ C is always set here
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CALGN( bcs 2f )
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CALGN( adr r4, 6f )
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CALGN( subs r2, r2, r3 ) @ C gets set
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#ifndef ARM_ALWAYS_BX
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CALGN( add pc, r4, ip, lsl #(ARM_BX_ALIGN_LOG2 - 2))
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#else
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CALGN( add r4, r4, ip, lsl #(ARM_BX_ALIGN_LOG2 - 2))
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CALGN( bx r4 )
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#endif
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PLD( pld [r1, #0] )
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2: PLD( subs r2, r2, #96 )
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PLD( pld [r1, #28] )
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PLD( blt 4f )
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PLD( pld [r1, #60] )
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PLD( pld [r1, #92] )
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3: PLD( pld [r1, #124] )
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4: ldmia r1!, {r3, r4, r5, r6, r7, r8, ip, lr}
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subs r2, r2, #32
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stmia r0!, {r3, r4, r5, r6, r7, r8, ip, lr}
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bge 3b
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PLD( cmn r2, #96 )
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PLD( bge 4b )
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5: ands ip, r2, #28
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rsb ip, ip, #32
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#ifndef ARM_ALWAYS_BX
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/* C is always clear here. */
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addne pc, pc, ip, lsl #(ARM_BX_ALIGN_LOG2 - 2)
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b 7f
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#else
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beq 7f
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push {r10}
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cfi_adjust_cfa_offset (4)
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cfi_rel_offset (r10, 0)
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0: add r10, pc, ip, lsl #(ARM_BX_ALIGN_LOG2 - 2)
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/* If alignment is not perfect, then there will be some
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padding (nop) instructions between this BX and label 6.
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The computation above assumed that two instructions
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later is exactly the right spot. */
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add r10, #(6f - (0b + PC_OFS))
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bx r10
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#endif
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.p2align ARM_BX_ALIGN_LOG2
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6: nop
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.p2align ARM_BX_ALIGN_LOG2
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ldr r3, [r1], #4
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.p2align ARM_BX_ALIGN_LOG2
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ldr r4, [r1], #4
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.p2align ARM_BX_ALIGN_LOG2
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ldr r5, [r1], #4
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.p2align ARM_BX_ALIGN_LOG2
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ldr r6, [r1], #4
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.p2align ARM_BX_ALIGN_LOG2
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ldr r7, [r1], #4
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.p2align ARM_BX_ALIGN_LOG2
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ldr r8, [r1], #4
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.p2align ARM_BX_ALIGN_LOG2
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ldr lr, [r1], #4
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#ifndef ARM_ALWAYS_BX
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add pc, pc, ip, lsl #(ARM_BX_ALIGN_LOG2 - 2)
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nop
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#else
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0: add r10, pc, ip, lsl #(ARM_BX_ALIGN_LOG2 - 2)
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/* If alignment is not perfect, then there will be some
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padding (nop) instructions between this BX and label 66.
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The computation above assumed that two instructions
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later is exactly the right spot. */
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add r10, #(66f - (0b + PC_OFS))
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bx r10
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#endif
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.p2align ARM_BX_ALIGN_LOG2
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66: nop
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.p2align ARM_BX_ALIGN_LOG2
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str r3, [r0], #4
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.p2align ARM_BX_ALIGN_LOG2
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str r4, [r0], #4
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.p2align ARM_BX_ALIGN_LOG2
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str r5, [r0], #4
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.p2align ARM_BX_ALIGN_LOG2
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str r6, [r0], #4
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.p2align ARM_BX_ALIGN_LOG2
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str r7, [r0], #4
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.p2align ARM_BX_ALIGN_LOG2
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str r8, [r0], #4
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.p2align ARM_BX_ALIGN_LOG2
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str lr, [r0], #4
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#ifdef ARM_ALWAYS_BX
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pop {r10}
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cfi_adjust_cfa_offset (-4)
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cfi_restore (r10)
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#endif
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CALGN( bcs 2b )
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7: pop {r5 - r8}
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cfi_adjust_cfa_offset (-16)
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cfi_restore (r5)
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cfi_restore (r6)
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cfi_restore (r7)
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cfi_restore (r8)
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8: movs r2, r2, lsl #31
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ldrbne r3, [r1], #1
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ldrbcs r4, [r1], #1
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ldrbcs ip, [r1]
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strbne r3, [r0], #1
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strbcs r4, [r0], #1
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strbcs ip, [r0]
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#if ((defined (__ARM_ARCH_4T__) && defined(__THUMB_INTERWORK__)) \
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|| defined (ARM_ALWAYS_BX))
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pop {r0, r4, lr}
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cfi_adjust_cfa_offset (-12)
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cfi_restore (r4)
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cfi_restore (lr)
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bx lr
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#else
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pop {r0, r4, pc}
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#endif
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cfi_restore_state
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9: rsb ip, ip, #4
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cmp ip, #2
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ldrbgt r3, [r1], #1
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ldrbge r4, [r1], #1
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ldrb lr, [r1], #1
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strbgt r3, [r0], #1
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strbge r4, [r0], #1
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subs r2, r2, ip
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strb lr, [r0], #1
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blt 8b
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ands ip, r1, #3
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beq 1b
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10: bic r1, r1, #3
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cmp ip, #2
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ldr lr, [r1], #4
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beq 17f
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bgt 18f
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.macro forward_copy_shift pull push
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subs r2, r2, #28
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blt 14f
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CALGN( ands ip, r1, #31 )
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CALGN( rsb ip, ip, #32 )
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CALGN( sbcsne r4, ip, r2 ) @ C is always set here
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CALGN( subcc r2, r2, ip )
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CALGN( bcc 15f )
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11: push {r5 - r8, r10}
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cfi_adjust_cfa_offset (20)
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cfi_rel_offset (r5, 0)
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cfi_rel_offset (r6, 4)
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cfi_rel_offset (r7, 8)
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cfi_rel_offset (r8, 12)
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cfi_rel_offset (r10, 16)
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PLD( pld [r1, #0] )
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PLD( subs r2, r2, #96 )
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PLD( pld [r1, #28] )
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PLD( blt 13f )
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PLD( pld [r1, #60] )
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PLD( pld [r1, #92] )
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12: PLD( pld [r1, #124] )
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13: ldmia r1!, {r4, r5, r6, r7}
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mov r3, lr, PULL #\pull
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subs r2, r2, #32
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ldmia r1!, {r8, r10, ip, lr}
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orr r3, r3, r4, PUSH #\push
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mov r4, r4, PULL #\pull
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orr r4, r4, r5, PUSH #\push
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mov r5, r5, PULL #\pull
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orr r5, r5, r6, PUSH #\push
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mov r6, r6, PULL #\pull
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orr r6, r6, r7, PUSH #\push
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mov r7, r7, PULL #\pull
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orr r7, r7, r8, PUSH #\push
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mov r8, r8, PULL #\pull
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orr r8, r8, r10, PUSH #\push
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mov r10, r10, PULL #\pull
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orr r10, r10, ip, PUSH #\push
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mov ip, ip, PULL #\pull
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orr ip, ip, lr, PUSH #\push
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stmia r0!, {r3, r4, r5, r6, r7, r8, r10, ip}
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bge 12b
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PLD( cmn r2, #96 )
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PLD( bge 13b )
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pop {r5 - r8, r10}
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cfi_adjust_cfa_offset (-20)
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cfi_restore (r5)
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cfi_restore (r6)
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cfi_restore (r7)
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cfi_restore (r8)
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cfi_restore (r10)
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14: ands ip, r2, #28
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beq 16f
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15: mov r3, lr, PULL #\pull
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ldr lr, [r1], #4
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subs ip, ip, #4
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orr r3, r3, lr, PUSH #\push
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str r3, [r0], #4
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bgt 15b
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CALGN( cmp r2, #0 )
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CALGN( bge 11b )
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16: sub r1, r1, #(\push / 8)
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b 8b
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.endm
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forward_copy_shift pull=8 push=24
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17: forward_copy_shift pull=16 push=16
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18: forward_copy_shift pull=24 push=8
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END(memcpy)
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libc_hidden_builtin_def (memcpy)
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