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5bc100bd4b
log1pf is quite register-intensive - use fewer registers for the polynomial, and make various changes to shorten dependency chains in parent routines. There is now no spilling with GCC 14. Accuracy moves around a little - comments adjusted accordingly but does not require regen-ulps. Use the helper in log1pf as well, instead of having separate implementations. The more accurate polynomial means special-casing can be simplified, and the shorter dependency chain avoids the usual dance around v0, which is otherwise difficult. There is a small duplication of vectors containing 1.0f (or 0x3f800000) - GCC is not currently able to efficiently handle values which fit in FMOV but not MOVI, and are reinterpreted to integer. There may be potential for more optimisation if this is fixed. Reviewed-by: Wilco Dijkstra <Wilco.Dijkstra@arm.com>
77 lines
2.9 KiB
C
77 lines
2.9 KiB
C
/* Single-precision vector (Advanced SIMD) acosh function
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Copyright (C) 2024 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<https://www.gnu.org/licenses/>. */
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#include "v_log1pf_inline.h"
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#define SquareLim 0x1p64
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const static struct data
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{
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struct v_log1pf_data log1pf_consts;
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uint32x4_t one;
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} data = { .log1pf_consts = V_LOG1PF_CONSTANTS_TABLE, .one = V4 (0x3f800000) };
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#define Thresh vdup_n_u16 (0x2000) /* top(asuint(SquareLim) - asuint(1)). */
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static float32x4_t NOINLINE VPCS_ATTR
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special_case (float32x4_t x, float32x4_t y, uint16x4_t special,
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const struct v_log1pf_data *d)
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{
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return v_call_f32 (acoshf, x, log1pf_inline (y, d), vmovl_u16 (special));
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}
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/* Vector approximation for single-precision acosh, based on log1p. Maximum
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error depends on WANT_SIMD_EXCEPT. With SIMD fp exceptions enabled, it
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is 3.00 ULP:
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_ZGVnN4v_acoshf(0x1.01df3ap+0) got 0x1.ef0a82p-4
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want 0x1.ef0a7cp-4.
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With exceptions disabled, we can compute u with a shorter dependency chain,
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which gives maximum error of 3.22 ULP:
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_ZGVnN4v_acoshf(0x1.007ef2p+0) got 0x1.fdcdccp-5
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want 0x1.fdcdd2p-5. */
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VPCS_ATTR float32x4_t NOINLINE V_NAME_F1 (acosh) (float32x4_t x)
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{
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const struct data *d = ptr_barrier (&data);
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uint32x4_t ix = vreinterpretq_u32_f32 (x);
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uint16x4_t special = vcge_u16 (vsubhn_u32 (ix, d->one), Thresh);
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#if WANT_SIMD_EXCEPT
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/* Mask special lanes with 1 to side-step spurious invalid or overflow. Use
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only xm1 to calculate u, as operating on x will trigger invalid for NaN.
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Widening sign-extend special predicate in order to mask with it. */
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uint32x4_t p
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= vreinterpretq_u32_s32 (vmovl_s16 (vreinterpret_s16_u16 (special)));
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float32x4_t xm1 = v_zerofy_f32 (vsubq_f32 (x, v_f32 (1)), p);
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float32x4_t u = vfmaq_f32 (vaddq_f32 (xm1, xm1), xm1, xm1);
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#else
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float32x4_t xm1 = vsubq_f32 (x, vreinterpretq_f32_u32 (d->one));
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float32x4_t u
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= vmulq_f32 (xm1, vaddq_f32 (x, vreinterpretq_f32_u32 (d->one)));
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#endif
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float32x4_t y = vaddq_f32 (xm1, vsqrtq_f32 (u));
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if (__glibc_unlikely (v_any_u16h (special)))
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return special_case (x, y, special, &d->log1pf_consts);
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return log1pf_inline (y, &d->log1pf_consts);
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}
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libmvec_hidden_def (V_NAME_F1 (acosh))
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HALF_WIDTH_ALIAS_F1 (acosh)
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