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By using a combination of mask-and-add instead of the shift-based index calculation the routines can share the same table as other variants with no performance degradation. The tables change name because of other changes in downstream AOR. Reviewed-by: Wilco Dijkstra <Wilco.Dijkstra@arm.com>
142 lines
4.0 KiB
C
142 lines
4.0 KiB
C
/* Configuration for libmvec routines.
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Copyright (C) 2023-2024 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<https://www.gnu.org/licenses/>. */
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#ifndef _VECMATH_CONFIG_H
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#define _VECMATH_CONFIG_H
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#include <math_private.h>
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/* Deprecated config option from Arm Optimized Routines which ensures
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fp exceptions are correctly triggered. This is not intended to be
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supported in GLIBC, however we keep it for ease of development. */
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#define WANT_SIMD_EXCEPT 0
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/* Return ptr but hide its value from the compiler so accesses through it
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cannot be optimized based on the contents. */
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#define ptr_barrier(ptr) \
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({ \
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__typeof (ptr) __ptr = (ptr); \
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__asm("" : "+r"(__ptr)); \
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__ptr; \
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})
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#define V_LOG_POLY_ORDER 6
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#define V_LOG_TABLE_BITS 7
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extern const struct v_log_data
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{
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/* Shared data for vector log and log-derived routines (e.g. asinh). */
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double poly[V_LOG_POLY_ORDER - 1];
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double ln2;
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struct
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{
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double invc, logc;
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} table[1 << V_LOG_TABLE_BITS];
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} __v_log_data attribute_hidden;
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#define V_EXP_TAIL_TABLE_BITS 8
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extern const uint64_t __v_exp_tail_data[1 << V_EXP_TAIL_TABLE_BITS] attribute_hidden;
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#define V_EXP_TABLE_BITS 7
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extern const uint64_t __v_exp_data[1 << V_EXP_TABLE_BITS] attribute_hidden;
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#define V_LOG2_TABLE_BITS 7
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extern const struct v_log2_data
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{
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double poly[5];
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double invln2;
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struct
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{
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double invc, log2c;
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} table[1 << V_LOG2_TABLE_BITS];
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} __v_log2_data attribute_hidden;
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#define V_LOG10_TABLE_BITS 7
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extern const struct v_log10_data
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{
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double poly[5];
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double invln10, log10_2;
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struct
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{
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double invc, log10c;
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} table[1 << V_LOG10_TABLE_BITS];
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} __v_log10_data attribute_hidden;
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extern const struct v_erff_data
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{
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struct
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{
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float erf, scale;
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} tab[513];
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} __v_erff_data attribute_hidden;
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extern const struct v_erf_data
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{
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struct
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{
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double erf, scale;
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} tab[769];
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} __v_erf_data attribute_hidden;
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extern const struct v_erfc_data
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{
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struct
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{
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double erfc, scale;
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} tab[3488];
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} __v_erfc_data attribute_hidden;
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extern const struct v_erfcf_data
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{
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struct
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{
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float erfc, scale;
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} tab[645];
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} __v_erfcf_data attribute_hidden;
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/* Some data for AdvSIMD and SVE pow's internal exp and log. */
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#define V_POW_EXP_TABLE_BITS 8
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extern const struct v_pow_exp_data
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{
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double poly[3];
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double n_over_ln2, ln2_over_n_hi, ln2_over_n_lo, shift;
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uint64_t sbits[1 << V_POW_EXP_TABLE_BITS];
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} __v_pow_exp_data attribute_hidden;
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#define V_POW_LOG_TABLE_BITS 7
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extern const struct v_pow_log_data
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{
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double poly[7]; /* First coefficient is 1. */
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double ln2_hi, ln2_lo;
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double invc[1 << V_POW_LOG_TABLE_BITS];
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double logc[1 << V_POW_LOG_TABLE_BITS];
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double logctail[1 << V_POW_LOG_TABLE_BITS];
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} __v_pow_log_data attribute_hidden;
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/* Some data for SVE powf's internal exp and log. */
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#define V_POWF_EXP2_TABLE_BITS 5
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#define V_POWF_EXP2_N (1 << V_POWF_EXP2_TABLE_BITS)
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#define V_POWF_LOG2_TABLE_BITS 5
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#define V_POWF_LOG2_N (1 << V_POWF_LOG2_TABLE_BITS)
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extern const struct v_powf_data
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{
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double invc[V_POWF_LOG2_N];
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double logc[V_POWF_LOG2_N];
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uint64_t scale[V_POWF_EXP2_N];
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} __v_powf_data attribute_hidden;
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#endif
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