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https://sourceware.org/git/glibc.git
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4372980f58
I've moved the TILE-Gx and TILEPro ports to the main sysdeps hierarchy,
along with the linux-generic ports infrastructure. Beyond the README
update, the move was just
git mv ports/sysdeps/tile sysdeps/tile
git mv ports/sysdeps/unix/sysv/linux/tile \
sysdeps/unix/sysv/linux/tile
git mv ports/sysdeps/unix/sysv/linux/generic \
sysdeps/unix/sysv/linux/generic
I updated the relevant ChangeLogs along the lines of the ARM move
in commit c6bfe5c4d7 and tested the 64-bit tilegx build to confirm that
there were no changes in "objdump -dr" output in the shared objects.
90 lines
2.0 KiB
ArmAsm
90 lines
2.0 KiB
ArmAsm
/* Copyright (C) 2011-2014 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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Contributed by Chris Metcalf <cmetcalf@tilera.com>, 2011.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library. If not, see
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<http://www.gnu.org/licenses/>. */
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#include <sysdep.h>
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#include "ucontext_i.h"
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/* int swapcontext (ucontext_t *oucp, const ucontext_t *ucp) */
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.text
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ENTRY (__swapcontext)
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FEEDBACK_ENTER(__swapcontext)
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/* Set up a frame and save r0 and r1. */
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{
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ST sp, lr
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ADDI_PTR r11, sp, -(3 * REGSIZE)
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move r10, sp
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}
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ADDI_PTR sp, sp, -(4 * REGSIZE)
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cfi_def_cfa_offset (4 * REGSIZE)
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cfi_offset (lr, 0)
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{
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ST r11, r10
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ADDI_PTR r10, sp, (2 * REGSIZE)
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}
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{
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ST r10, r0
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ADDI_PTR r10, sp, (3 * REGSIZE)
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}
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ST r10, r1
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/* Save the current context. */
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jal __getcontext
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/* Tear down the frame and restore r0, r1, and lr. */
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{
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BNEZ r0, .Lerror
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ADDI_PTR r1, sp, 3 * REGSIZE
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}
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{
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LD r1, r1
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ADDI_PTR r0, sp, 2 * REGSIZE
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}
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{
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LD r0, r0
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ADDI_PTR sp, sp, 4 * REGSIZE
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}
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cfi_def_cfa_offset (0)
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{
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LD lr, sp
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ADDLI_PTR r10, r0, UC_REG(54)
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}
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/* Update the stored sp and lr. */
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{
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ST r10, sp
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ADDLI_PTR r10, r0, UC_REG(55)
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}
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ST r10, lr
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/* Tail-call setcontext to finish up. */
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{
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move r0, r1
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j __setcontext
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}
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.Lerror:
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ADDI_PTR sp, sp, 4 * REGSIZE
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cfi_def_cfa_offset (0)
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LD lr, sp
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jrp lr
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END (__swapcontext)
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weak_alias (__swapcontext, swapcontext)
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